2.1 ADC EVM Data Capture
New TI high-speed ADCs and DACs now have high-speed serial data that meets the JESD204C_B standard.
These devices are generally available on an EVM that connects directly to the TSW14J58EVM. The common
connector between the EVMs and the TSW14J58EVM is a Samtec high-speed, high-density FMC+ connector
(ASP-184329-01) suitable for high-speed differential pairs up to 32.5 Gbps. A common pinout for the connector
across a family of EVMs has been established. At present, the interface between the EVMs and the
TSW14J58EVM has defined connections for 32 high-speed differential data pairs (16 RX and 16 TX), 23 single-
ended signals, a single-ended SYNC, 5 differential spares, a differential SYNC and SYSREF, and four device
clock pairs (FPGA reference clock). The board has 10 spare USB2.0 interface signals, two FPGA reference
clock SMAs, three SYNC output SMAs, one external input trigger SMA, four reset switches, and 13 status LEDs.
The data format for JESD204C_B ADCs and DACs is a serialized format, where individual bits of the data
are presented on the serial pairs commonly referred to as lanes. Devices designed around the JESD204C_B
specification can have up to 16 lanes for transmitting or receiving data. The firmware in the FPGA on the
TSW14J58 is designed to accommodate any of TI's ADC or DAC operating with any number of lanes from 1 to
16.
The HSDC Pro GUI loads the FPGA with the appropriate firmware and a specific JESD204C_B configuration,
based on the ADC device selected in the device drop down window. Each ADC device that appears in this
window has an initialization file (.ini) associated to it. This .ini file contains JESD information, such as number
of lanes, number of converters, octets per frame, and other parameters. This information is loaded into the
FPGA registers after the user clicks on the capture button. After the parameters are loaded, synchronization is
established between the data converter and FPGA and valid data is then captured into the onboard memory.
See the
High-Speed Data Capture Pro GUI Software User's Guide
under the Technical Documents section for
more information. Several .ini files are available to allow the user to load predetermined ADC JESD204C_B
interfaces.
The TSW14J58 device can capture up to 1.536G 16-bit samples at a maximum line rate of 24 Gbps that are
stored inside the onboard DDR4 memory. The data size the user sets in the HSDC Pro GUI must be entered as
multiples of 480. To acquire data on a host PC, the FPGA reads the data from memory and transmits parallel
data to the onboard high-speed parallel-to-USB3.0 converter.
2.2 DAC EVM Pattern Generator
In pattern generator mode, the TSW14J58EVM generates desired test patterns for DAC EVMs under test.
These patterns are sent from the host PC over the USB interface to the TSW14J58. The FPGA stores the data
received into the onboard DDR4 memory. The data from the memory is then read by the FPGA, converted
to JESD204C_B serial format, then transmitted to a DAC EVM. The TSW14J58 can generate patterns up to
1.536G 16-bit samples at a line rate up to 24.5 Gbps.
There are GUIs available that come with several existing test patterns that can be download immediately. Like
the ADC capture mode, the DAC pattern generator mode uses .ini files to load predetermined JESD204C_B
interface information to the FPGA.
Functionality
SLWU094 – MARCH 2021
TSW14J58 JESD204C Data Capture and
Pattern Generator Card
5
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