Texas Instruments TSW14J58 JESD204C, User Manual, Page: 4 / 23

• Onboard FTDI FT4232H USB 2.0 device for FPGA JTAG interface (downloading firmware) and general
purpose I/O interface to onboard functions and FMC+
• Reference clocking for transceivers available through FMC+ port or SMAs
• Supported by TI HSDC PRO software
• FPGA firmware developed with Xilinx Vivado development tool.
– JESD RX IP core with support for:
• USB and JTAG reconfigurable JESD core parameters: L, M, K, F, HD, S, and more
• ILA configuration data accessible through USB and JTAG
• Lane alignment and character replacement enabled or disabled through USB and JTAG
– JESD TX IP core with support for:
• USB and JTAG reconfigurable JESD core parameters: L, M, K, F, HD, S, and more
• ILA configuration data accessible through USB and JTAG
• Dynamically reconfigurable Transceiver data rate.
– Serial lane operating range from 1 to 24.5 Gbps
Figure 2-2 shows a block diagram of the TSW14J58 EVM.
Power Regulators
USB 2.0
Port
EEPROM
EEPROM
JTAG
Connector
USB to Parallel
USB 3.0
Port
24 Gb DDR4 RAM
Xilinx Kintex Ultr FPGA
(Firmware)
FMC+ Connector
+5.5 VDC
Input
ADC, DAC or AFE EVM
JESD 204B Interface
Data, Device CLK,
SYSREF, SYNC, GPIO
GPIO
JTAG i/F
TSW14J58EVM
Figure 2-2. TSW14J58EVM Block Diagram
Functionality www.ti.com
4 TSW14J58 JESD204C Data Capture and
Pattern Generator Card SLWU094 – MARCH 2021
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