Texas Instruments TPS70151 Series, User Manual, Page: 10 / 28

Schematic
1-4 Introduction
1.3 Schematic
Figure1–2 shows the SLVP152 EVM schematic diagram.
Figure 1–2. SLVP152 EVM Universal LDO Tester Schematic Diagram
0.1
µ
F
VOUT2
ENABLE
7
DISCH
6
THRES
2
TRIG
8
VCC
1
GND
4
RESET
3
OUT
5
CTL
D1
DL4148
C1
J2
C6
+
C3
C8
C9
C10
1000 pF
TP9
3
VIN1
2
VIN1
7 SEQUENCE
8
GND
9
VIN2
10
VIN2
1
NC
11 NC
12
13
VOUT2
14
VSENSE2
16
PG_1
17
VSENSE1
18
VOUT1
19
VOUT1
20
NC
4
MR2
5
MR1
6 15
RESET
PwrPad
R5 10
R7 10
3
GND
1
VDD
2
1IN
4
2IN
8
REG
6
VCC
5
2OUT
7
1OUT
Q1
Si4410
Si4410
Q2
C11
1000 pF
DL4148
D2
DL4148
D3
R6 510
R8 510
+
C2
C4
J1
JP4
JP3
JP2
TP7
TP8
D4
Green
TP4
TP3
TP6
TP5
JP1
J3
TP11
TP12
TP13
R13
0
D5
RED
R11
0
TP10
+
C12
C14
TP17
R14
1.8K
TP14
TP16
JP5
JP6
+
C13
C15
TP15
U3
TPS70151PWP
VO1
GND
GND
VO2
4
3
2
1
VIN1
GND
GND
VIN2
1
2
3
4
Default Jumper Settings
JP1 2–3 = PG Controls MR2
JP3 Low – Enabled
JP4 1–2 = VO1 an first
100
µ
F
0.1
µ
F
TP1
VIN1
Sense
PG_1
GND
GND
VIN
TP2
VIN2
Sense
100
µ
F 0.1
µ
F
VCC
GND
1
2
U2
TPS2812
R3
5.1 k
Ω
R1
4.3 k
Ω
R2
10 k
Ω
1
µ
F
Enable
On
Off
S1 U1
TPS555D
C7
0.1
µ
F
10
µ
F
R9
2 k
Ω
R10
2 k
Ω
VO1
Sense
0.1
µ
F
33
µ
F
R12
3.3 k
Ω
VO2
Sense
0.1
µ
F
33
µ
F
R4
10 k
Ω
R24 R23 R22 R21 R20
JP16 JP15 JP14 JP13 JP12
JP1
1
JP10
JP9 JP8 JP7
R19 R18 R17 R16 R15
C5
0.1
µ
F