Texas Instruments TPS70151 Series User Manual Download | Manualshive

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Low Dropout, DualĆOutput

Linear Regulator EVM Using

the TPS70151

April 2000

Mixed-Signal Products

User’s Guide

SLVU025A

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Summary of Contents for TPS70151 Series

Page 1: ...Low Dropout Dual Output Linear Regulator EVM Using the TPS70151 April 2000 Mixed Signal Products User s Guide SLVU025A...

Page 2: ...this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Customers are responsible for their applications using TI...

Page 3: ...est Results Information About Cautions and Warnings This book may contain cautions and warnings This is an example of a caution statement A caution statement describes a situation that could potential...

Page 4: ...iv...

Page 5: ...1 2 Design Strategy 1 3 1 3 Schematic 1 4 1 4 Bill of Materials 1 5 1 5 Board Layout 1 7 2 EVM Adjustments and Test Points 2 1 2 1 Adjustment by Switch and Jumper 2 2 2 2 Adjustment Through Component...

Page 6: ...g Time 4 2 4 2 No Load Full Load 500 mA Transition With CO 33 F POSCAP LDO Response Time 4 2 4 3 No Load Full Load 500 mA Transition With CO 33 F POSCAP Maximum Transient Droop Voltage 4 3 4 4 Timing...

Page 7: ...lications with power sequencing requirement Differentiated features such as SVS supervisory circuit manual reset inputs and enable function provide a complete system solution Moreover with its low qui...

Page 8: ...acitor for stabilization Figure 1 1 shows the circuit of a typical LDO application Figure 1 1 Typical LDO Application _ Control _ R1 R2 Q1 Vref LDO CO VO Load _ VCC In the LDO application shown in Fig...

Page 9: ...ontains a TPS70151 Regulator 1 provides an output voltage of 3 3 V and a maximum output current of 500 mA Regulator 2 provides an output voltage of 1 8 V and a maximum output current of 250 mA Table 1...

Page 10: ...Si4410 Q2 C11 1000 pF DL4148 D2 DL4148 D3 R6 510 R8 510 C2 C4 J1 JP4 JP3 JP2 TP7 TP8 D4 Green TP4 TP3 TP6 TP5 JP1 J3 TP11 TP12 TP13 R13 0 D5 RED R11 0 TP10 C12 C14 TP17 R14 1 8K TP14 TP16 JP5 JP6 C13...

Page 11: ...32RC TR Diode LED red 1 7 V 40 mcd SM Lumex 1210 J1 3 2 ED1516 Terminal block 4 pin 6 A 3 5 mm OST 3 5 mm J2 1 ED1514 Terminal block 2 pin 6A 3 5 mm OST 3 5 mm JP1 4 2 PTC36SAAN Header single row stra...

Page 12: ...h 1P2T slide PC mount E Switch 0 1 TP1 2 16 17 4 131 4244 00 Adaptor 3 5 mm probe clip or 131 5031 00 Tektronix TP3 15 13 240 345 Test point red Farnell U1 1 TLC555D IC timer TI SO8 U2 1 TPS2812D IC M...

Page 13: ...Board Layout 1 7 Introduction 1 5 Board Layout Figures 1 3 through 1 5 show the board layout for the SLVP125 EVM Figure 1 3 Top Layer Top Layer Figure 1 4 Bottom Layer top view Bottom Layer Top View...

Page 14: ...Board Layout 1 8 Introduction Figure 1 5 Assembly Drawing top assembly Top Assembly Dual Output LDO EVM SLVP152...

Page 15: ...ollowing EVM adjustment modes Adjustment by switch and jumper Adjustment through changing components Figure 2 1 shows the locations of the adjustment points on the board Topic Page 2 1 Adjustment by S...

Page 16: ...83 of max output voltage JP5 Shorted bypass transient generator for regulator 1 Allows continuous load through onboard load resistors on regulator 1 Open engage transient generator for regulator 1 Al...

Page 17: ...C R1 ton 2D 1 0 693 D C R2 ton 1 D 0 693 D C R2 ton 1 D 0 693 D C Note ton desired load on time s D on time duty cycle C total capacitance in circuit 1 uF RH1 RH2 Timer resistors value refer to schema...

Page 18: ...cted Jumpers JP7 JP11 and JP12 JP16 vary the current through the onboard resistors from 0 to max load current for regulator 1 and regulator 2 respectively Figure 2 1 Test Setup Power Supply 5 V 1 A Su...

Page 19: ...3 1 Circuit Design Circuit Design This chapter describes the LDO circuit design procedure Topic Page 3 1 Temperature Considerations 3 2 3 2 ESR and Transient Response 3 2 Chapter 3...

Page 20: ...r the package i e 32 6 C W for the 20 terminal TSSOP package TA is the ambient temperature The regulator dissipation is calculated using PD VIN VOUT IOUT 3 2 ESR and Transient Response LDOs typically...

Page 21: ...shown as VESR in Figure 3 2 When CO is conducting current to the load initial voltage at the load will be VO V CO VESR DuetothedischargeofCO theoutputvoltageVO willdrop continuously until the respons...

Page 22: ...Transient Response 3 4 Circuit Design Figure 3 3 Correlation of Different ESRs and Their Influence to the Regulation of VO at a Load Step From Low to High Output Current ESR 1 ESR 2 ESR 3 3 1 2 t1 t2...

Page 23: ...4 1 Test Results Test Results This chapter presents laboratory test results for the TPS70151 LDO design Topic Page 4 1 Test Results 4 2 Chapter 4...

Page 24: ...regulator 1 output channel 2 is regulator 2 output and channel 4 is RESET Channel 3 is PG_1 in figures 4 4 through 4 8 Channel 3 is MR1 in figure 4 9 Figure 4 1 No Load Full Load 500 mA Transition Wi...

Page 25: ...ent Droop Voltage The maximum transient droop voltage is 56 mV Figure 4 4 Timing When SEQUENCE Low VIN1 VIN2 at 5V and both VOUT1 CH1 and VOUT2 CH2 have no load EN is pulsed with a fast pulse VOUT1 po...

Page 26: ...CE low PG_1 CH3 tied to MR1 goes high when VOUT1 reaches 95 of regulated voltage After a 120 ms delay RESET CH4 is being driven by both VOUT1 and VOUT2 power good Figure 4 6 Timing When SEQUENCE High...

Page 27: ...CH1 faults out due to current limit The VOUT1 fault causes PG_1 CH3 tied to MR1 to go low MR1 causes RESET CH4 to go low Figure 4 8 Timing When SEQUENCE High and VOUT2 Faults Out When SEQUENCE high a...

Page 28: ...4 6 Test Results Figure 4 9 Timing When MR Is Toggled MR1 CH3 is taken low and RESET CH4 follows MR1 VOUT1 CH1 and VOUT2 CH2 are unaffected All results are consistent with those reported in the SLVS2...

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