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Board Layout
3.1
EVM Layout
Figure 3
through
Figure 6
illustrate the PCB layout for this EVM.
Figure 3. Board Layout (Top Layer)
Figure 4. Board Layout (Second Layer)
Figure 5. Board Layout (Third Layer)
Figure 6. Board Layout (Bottom Layer)
5
SLVUA85 – June 2014
TPS65261EVM-650 PMIC 3-A, 2-A, 2-A Output Current Evaluation Module
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