Texas Instruments TPS65261EVM-650 User Manual Download Page 2

Background

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Background

The TPS65261 PMIC is a triple 3-A, 2-A, 2-A output current, synchronous step-down (buck) converter with
an operational range of 4.5 V to 18 V. The TPS65261 features an automatic power sequence with
connecting MODE pin to V7V and configuring EN1/2/3 pins. The device also features an open drain
RESET signal to monitor power down. The TPS65261 operates in pulse skipping mode (PSM) light load.

As there are many possible options to set the converters,

Table 1

presents the performance specification

summary for the EVM.

Table 1. Summary of Performance

Test Conditions

Performance

VIN = 4.5 V to 18 V

BUCK1, 1.2 V, up to 3 A

f

SW

= 600 kHz

BUCK2, 3.3 V, up to 2 A

(25°C ambient)

BUCK3, 1.8 V, up to 2 A

RESET, pull low when VDIV lower than 1.23 V

This evaluation module is designed to provide access to the features of the TPS65261. Some
modifications can be made to this module to test performance at different input and output voltages,
current and switching frequency. Contact the TI Field Applications group for advice on these matters.

All trademarks are the property of their respective owners.

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TPS65261EVM-650 PMIC 3-A, 2-A, 2-A Output Current Evaluation Module

SLVUA85 – June 2014

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Copyright © 2014, Texas Instruments Incorporated

Summary of Contents for TPS65261EVM-650

Page 1: ...65261 Schematic 3 3 Board Layout 4 4 Bench Test Setup Conditions 6 5 Power Up Procedure 7 6 Bill of Materials 8 List of Figures 1 TPS65261 Schematic 3 2 Component Placement Top Layer 4 3 Board Layout...

Page 2: ...r the EVM Table 1 Summary of Performance Test Conditions Performance VIN 4 5 V to 18 V BUCK1 1 2 V up to 3 A fSW 600 kHz BUCK2 3 3 V up to 2 A 25 C ambient BUCK3 1 8 V up to 2 A RESET pull low when VD...

Page 3: ...ND 0 01 F C19 0 01 F C20 GND 73 2k R17 20 0k R7 GND 100k R11 TP9 TP8 100k R9 V7V V7V 1 2 3 J6 100k R22 51k R26 GND EN2 GND DNI C27 1 2 3 J7 100k R23 51k R27 GND EN3 GND DNI C28 V7V GND 10 0k R19 20 0k...

Page 4: ...e 2 illustrates the PCB layout for this EVM Figure 2 Component Placement Top Layer 4 TPS65261EVM 650 PMIC 3 A 2 A 2 A Output Current Evaluation Module SLVUA85 June 2014 Submit Documentation Feedback C...

Page 5: ...VM Figure 3 Board Layout Top Layer Figure 4 Board Layout Second Layer Figure 5 Board Layout Third Layer Figure 6 Board Layout Bottom Layer 5 SLVUA85 June 2014 TPS65261EVM 650 PMIC 3 A 2 A 2 A Output C...

Page 6: ...escription and jumper placement on the EVM Figure 7 Header Descriptions and Jumper Placement Test points A LX of VOUT1 B LX of VOUT2 C LX of VOUT3 VOUT1 VOUT2 VOUT3 VIN PGOOD RESET V7V 6 TPS65261EVM 6...

Page 7: ...ble VOUT3 connect EN3 to VIN through a 100 k resistor to enable VOUT3 leave open to enable VOUT3 J8 Mode Power sequencing mode control pin Connect this pin to GND to set power sequence with dedicated...

Page 8: ...Printable Labels 0 650 W x 0 200 H 10 000 per roll PCB Label 0 650 H x 0 200 W THT 14 423 10 Brady R1 R2 R8 R10 R15 6 0 RES 0 ohm 5 0 1W 0603 0603 CRCW06030000Z0EA Vishay Dale R16 R3 R7 R20 3 20 0k RE...

Page 9: ...sponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related inf...

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