Texas Instruments TPS543320EVM, User Manual

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3.3 Output Voltage Regulation
Figure 3-5 and Figure 3-6 show the load and line regulation for U1. Figure 3-7 and Figure 3-8 show the load and
line regulation for U2.
I
OUT
(A)
V
O
U
T
(
V
)
0 0.5 1 1.5 2 2.5 3
1.81
1.812
1.814
1.816
1.818
1.82
V
IN
= 5 V
V
IN
= 12 V
V
IN
= 15 V
V
IN
= 18 V
Figure 3-5. U1 Load Regulation
V
IN
(V)
V
OU
T
(V
)
5 7 9 11 13 15 17 18
1.81
1.812
1.814
1.816
1.818
1.82
I
OUT
= 0 A
I
OUT
= 1.5 A
I
OUT
= 3 A
Figure 3-6. U1 Line Regulation
I
OUT
(A)
V
O
U
T
(
V
)
0 0.5 1 1.5 2 2.5 3
3.3
3.305
3.31
3.315
3.32
V
IN
= 5 V
V
IN
= 12 V
V
IN
= 18 V
Figure 3-7. U2 Load Regulation
V
IN
(V)
V
OU
T
(V
)
5 7 9 11 13 15 17 18
3.3
3.305
3.31
3.315
3.32
I
OUT
= 0 A
I
OUT
= 1.5 A
I
OUT
= 3 A
Figure 3-8. U2 Line Regulation
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SLVUC07A – DECEMBER 2020 – REVISED MAY 2021
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