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SPRUFH2

— TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Asynchronous

Receiver/Transmitter (UART) Users Guide

This document describes the universal asynchronous

receiver/transmitter (UART) peripheral in the TMS320DM36x Digital Media System-on-Chip
(DMSoC). The UART peripheral performs serial-to-parallel conversion on data received from a
peripheral device, and parallel-to-serial conversion on data received from the CPU.

SPRUFH3

— TMS320DM36x Digital Media System-on-Chip (DMSoC) Inter-Integrated Circuit (I2C)

Peripheral Users Guide

This document describes the inter-integrated circuit (I2C) peripheral in the

TMS320DM36x Digital Media System-on-Chip (DMSoC). The I2C peripheral provides an interface
between the DMSoC and other devices compliant with the I2C-bus specification and connected by
way of an I2C-bus. External components attached to this 2-wire serial bus can transmit and receive
up to 8-bit wide data to and from the DMSoC through the I2C peripheral. This document assumes
the reader is familiar with the I2C-bus specification.

SPRUFH4

TMS320DM36x Digital Media System-on-Chip (DMSoC) Memory Stick Controller Users

Guide This document This document describes the memory stick controller in the TMS320DM36x
Digital Media System-on-Chip (DMSoC). Memory Stick cards are used in a number of applications
to provide removable data storage. The memory stick controller provides an interface to external
Memory Stick cards. The communication between the controller and the cards is performed by the
Memory Stick protocol.

SPRUFH5

— TMS320DM36x Digital Media System-on-Chip (DMSoC) Multimedia Card (MMC)/Secure

Digital (SD) Card Controller Users Guide

This document describes the multimedia card

(MMC)/secure digital (SD) card controller in the TMS320DM36x Digital Media System-on-Chip
(DMSoC). The MMC/SD card is used in a number of applications to provide removable data
storage. The MMC/SD controller provides an interface to external MMC and SD cards. The
communication between the MMC/SD controller and MMC/SD card(s) is performed by the MMC/SD
protocol.

SPRUFH6

— TMS320DM36x Digital Media System-on-Chip (DMSoC) Pulse-Width Modulator (PWM)

Users Guide

This document describes the pulse-width modulator (PWM) peripheral in the

TMS320DM36x Digital Media System-on-Chip (DMSoC).

SPRUFH7

— TMS320DM36x Digital Media System-on-Chip (DMSoC) Real-Time Out (RTO) Controller

Users Guide

This document describes the Real Time Out (RTO) controller in the TMS320DM36x

Digital Media System-on-Chip (DMSoC).

SPRUFH8

— TMS320DM36x Digital Media System-on-Chip (DMSoC) General-Purpose Input/Output

(GPIO) Users Guide

This document describes the general-purpose input/output (GPIO) peripheral

in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The GPIO peripheral provides
dedicated general-purpose pins that can be configured as either inputs or outputs. When configured
as an input, you can detect the state of the input by reading the state of an internal register. When
configured as an output, you can write to an internal register to control the state driven on the
output pin.

SPRUFH9

— TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Serial Bus (USB)

Controller Users Guide

This document describes the universal serial bus (USB) controller in the

TMS320DM36x Digital Media System-on-Chip (DMSoC). The USB controller supports data
throughput rates up to 480 Mbps. It provides a mechanism for data transfer between USB devices
and also supports host negotiation.

SPRUFI0

— TMS320DM36x Digital Media System-on-Chip (DMSoC) Enhanced Direct Memory

Access (EDMA) Controller Users Guide

This document describes the operation of the enhanced

direct memory access (EDMA3) controller in the TMS320DM36x Digital Media System-on-Chip
(DMSoC). The EDMA controller's primary purpose is to service user-programmed data transfers
between two memory-mapped slave endpoints on the DMSoC.

SPRUFI1

— TMS320DM36x Digital Media System-on-Chip (DMSoC) Asynchronous External Memory

Interface (EMIF) Users Guide

This document describes the asynchronous external memory

interface (EMIF) in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The EMIF supports
a glueless interface to a variety of external devices.

6

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SPRUFI7 – March 2009

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Summary of Contents for TMS320DM36X

Page 1: ...TMS320DM36x DMSoC Analog to Digital Converter ADC Interface User s Guide Literature Number SPRUFI7 March 2009 ...

Page 2: ...2 SPRUFI7 March 2009 Submit Documentation Feedback ...

Page 3: ...et Considerations 10 2 5 Interrupt Support 10 2 6 EDMA Event Support 11 2 7 Power Management 11 2 8 Emulation Considerations 11 3 Registers 11 3 1 ADCTL 12 3 2 CMPTGT 13 3 3 CMPLDAT 13 3 4 CMPUDAT 14 3 5 SETDIV 14 3 6 CHSEL 14 3 7 AD0DAT 15 3 8 AD1DAT 15 3 9 AD2DAT 16 3 10 AD3DAT 16 3 11 AD4DAT 16 3 12 AD5DAT 17 3 13 EMUCTRL 17 SPRUFI7 March 2009 Table of Contents 3 Submit Documentation Feedback ...

Page 4: ... interface Memory Map Registers 11 2 ADC Control ADCTL Field Descriptions 12 3 Comparator Target Channel CMPTGT Field Descriptions 13 4 Comparison A D Lower Data CMPLDAT Field Descriptions 13 5 Comparison A D Upper Data CMPUDAT Field Descriptions 14 6 Setup Divide Value for Start A D SETDIV Field Descriptions 14 7 CHSEL setting for Channel selection 15 8 Analog Input Channel Select CHSEL Field Des...

Page 5: ...s the Video Processing Front End VPFE in the TMS320DM36x Digital Media System on Chip DMSoC SPRUFG9 TMS320DM36x Digital Media System on Chip DMSoC Video Processing Back End VPBE Users Guide This document describes the Video Processing Back End VPBE in the TMS320DM36x Digital Media System on Chip DMSoC SPRUFH0 TMS320DM36x Digital Media System on Chip DMSoC 64 bit Timer Users Guide This document des...

Page 6: ...he MMC SD controller and MMC SD card s is performed by the MMC SD protocol SPRUFH6 TMS320DM36x Digital Media System on Chip DMSoC Pulse Width Modulator PWM Users Guide This document describes the pulse width modulator PWM peripheral in the TMS320DM36x Digital Media System on Chip DMSoC SPRUFH7 TMS320DM36x Digital Media System on Chip DMSoC Real Time Out RTO Controller Users Guide This document des...

Page 7: ...face in the TMS320DM36x Digital Media System on Chip DMSoC The primary audio modes that are supported by the McBSP are the AC97 and IIS modes In addition to the primary audio modes the McBSP supports general serial port receive and transmit operation SPRUFI4 TMS320DM36x Digital Media System on Chip DMSoC Universal Host Port Interface UHPI User s Guide This document describes the operation of the u...

Page 8: ...es to the ADC interface using 32 bit wide control registers accessible via the internal peripheral bus The DM36x ADC interface has following features Supports six configurable analog Input Supports for successive approximation type 10 bit A D converter Programmable sampling conversion time base clock is AUXCLK Supports channel select by auto scan conversion Supports mode select by one shot mode or...

Page 9: ... operation see Section 2 3 2 In one shot mode operation the ADC interface does not run continuously and A D conversion terminates when scanning is completed For one shot mode operation the ADC interface should first be configured for scan mode SCNMD and comparator mode CMPMD in ADC interface control register ADCTL along with other configuration options The ADC interface sets the BUSY bit in ADCTL ...

Page 10: ... sample conversion If user change configuration then user need to wait at least a time which defined by SETDIV register after writing 0 into START bit The ADC interface can also stopped during the free run mode operatioor by reconfiguring it to one shot mode using the SCNMD bit in ADCTL register A software reset such as a reset generated by the emulator causes the ADC interface registers to return...

Page 11: ...ime Restart with the setting condition after the suspend time Table 1 lists the memory mapped registers for the analog to digital Controller ADC interface See the device specific data manual for the memory address of these registers Table 1 ADC interface Memory Map Registers Offset Register Description Location 0x0 ADCTL Control register Section 3 1 0x4 CMPTGT Comparator target channel Section 3 2...

Page 12: ... bit 0 If the value of A D input data is larger or smaller than the comparative data a comparator interrupt is generated ADC input data CMPLDAT or ADC input data CMPUDAT 1 If the value of A D input data is within the range of the comparative data a comparator interrupt is generated CMPLDAT ADC input data CMPUDAT 3 SCNFLG Scan interrupt flag clear bit Writing 1 into this bit clears the scan interru...

Page 13: ...nversion The analog input that has written 1 into CMPTGT is the target of the comparator The comparison A D lower data CMPLDAT register is shown in Figure 4 and described in Table 4 Figure 4 Comparison A D Lower Data CMPLDAT Register 31 10 9 0 Reserved CMPLDAT R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 Comparison A D Lower Data CMPLDAT Field Descriptions Bit Field Valu...

Page 14: ...riod SET_DIV 15 0 1 2 A D conversion time Peripheral CLK period SET_DIV 5 0 1 24 Note A D conversion time can t be less than 6us Figure 6 Setup Divide Value for Start A D SETDIV Register 31 16 Reserved R 0 15 0 SETDIV R W 0xFFFF LEGEND R W Read Write R Read only n value after reset Table 6 Setup Divide Value for Start A D SETDIV Field Descriptions Bit Field Value Description 31 16 Reserved 0 Any w...

Page 15: ...unselected 1 Analog Input selected The A D conversion data 0 AD0DAT register is shown in Figure 8 and descried in Table 9 Figure 8 A D Conversion Data 0 AD0DAT Register 31 10 9 0 Reserved AD0DAT R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 9 A D Conversion Data 0 AD0DAT Field Descriptions Bit Field Value Description 31 10 Reserved Any writes to these bit s must always have a...

Page 16: ...always have a value of 0 9 0 AD2DAT A D conversion data for channel 2 The A D conversion data 3 AD3DAT register is shown in Figure 11 and described in Table 12 Figure 11 A D Conversion Data 3 AD3DAT Register 31 10 9 0 Reserved AD3DAT R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 12 A D Conversion Data 3 AD3DAT Field Descriptions Bit Field Value Description 31 10 Reserved Any ...

Page 17: ...and described in Table 15 Figure 14 Emulation Control EMUCTRL Register 31 16 Reserved R 0 15 3 2 1 0 Reserved RT_SEL SOFT FREE R 0 R 0 R 1 R W 1 LEGEND R W Read Write R Read only n value after reset Table 15 Emulation Control EMUCTRL Field Descriptions Bit Field Value Description 31 2 Reserved Any writes to these bit s must always have a value of 0 2 RT_SEL 0 Support only emulation suspend 1 SOFT ...

Page 18: ...ice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertis...

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