100
C66x CorePac
Copyright 2012 Texas Instruments Incorporated
SPRS689D—March 2012
Multicore Fixed and Floating-Point System-on-Chip
TMS320C6670
5.1.2 L1D Memory
The L1D memory configuration for the C6670 device is as follows:
•
Region 0 size is 0K bytes (disabled)
•
Region 1 size is 32K bytes with no wait states
shows the available SRAM/cache configurations for L1D.
Figure 5-3
L1D Memory Configurations
L1D Me
m
or
y
00
F
0 0000h
00
F
0
4
000h
00
F
0 6000h
00
F
0 7000h
00
F
0 8000h
1/2
SRAM
2
-
Wa
y
Cache
3/
4
SRAM
7/8
SRAM
A
ll
SRAM
000
001
010
011
100
B
l
oc
k
Base
Address
L1D Mode B
i
ts
4
K b
y
tes
8K b
y
tes
16K b
y
tes
4
K b
y
tes
2
-
Wa
y
Cache
2
-
Wa
y
Cache
2
-
Wa
y
Cache
Summary of Contents for TMS320C6670
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