RGRXD[3:0]
(B)
RGRXCTL
(B)
RGRXC
(at DSP)
(A)
5
RXERR
RXDV
1st Half-byte
2nd Half-byte
RGRXD[7:4]
RGRXD[3:0]
2
3
1
4
4
6
SPRS276M – MAY 2005 – REVISED MARCH 2012
Table 7-86. Timing Requirements for EMAC RGMII Input Receive for 10/100/1000 Mbps
(1)
(see
-720
-850
A-1000/-1000
NO.
UNIT
-1200
MIN
MAX
Setup time, receive selected signals valid before RGRXC (at DSP)
5
t
su(RGRXD-RGRXCH)
1.0
ns
high/low
6
t
h(RGRXCH-RGRXD)
Hold time, receive selected signals valid after RGRXC (at DSP) high/low
1.0
ns
(1)
For RGMII, receive selected signals include: RGRXD[3:0] and RGRXCTL.
A.
RGRXC must be externally delayed relative to the data and control pins.
B.
Data and control information is received using both edges of the clocks. RGRXD[3:0] carries data bits 3-0 on the
rising edge of RGRXC and data bits 7-4 on the falling edge of RGRXC. Similarly, RGRXCTL carries RXDV on rising
edge of RGRXC and RXERR on falling edge.
Figure 7-69. EMAC Receive Interface Timing [RGMII Operation]
Table 7-87. Switching Characteristics Over Recommended Operating Conditions for RGTXC - RGMII
Operation for 10/100/1000 Mbit/s
(see
-720
-850
A-1000/-1000
NO.
UNIT
-1200
MIN
MAX
10 Mbps
360
440
1
t
c(RGTXC)
Cycle time, RGTXC
100 Mbps
36
44
ns
1000 Mbps
7.2
8.8
10 Mbps
0.40*t
c(RGTXC)
0.60*t
c(RGTXC)
2
t
w(RGTXCH)
Pulse duration, RGTXC high
100 Mbps
0.40*t
c(RGTXC)
0.60*t
c(RGTXC)
ns
1000 Mbps
0.45*t
c(RGTXC)
0.55*t
c(RGTXC)
10 Mbps
0.40*t
c(RGTXC)
0.60*t
c(RGTXC)
3
t
w(RGTXCL)
Pulse duration, RGTXC low
100 Mbps
0.40*t
c(RGTXC)
0.60*t
c(RGTXC)
ns
1000 Mbps
0.45*t
c(RGTXC)
0.55*t
c(RGTXC)
10 Mbps
0.75
4
t
t(RGTXC)
Transition time, RGTXC
100 Mbps
0.75
ns
1000 Mbps
0.75
Copyright © 2005–2012, Texas Instruments Incorporated
C64x+ Peripheral Information and Electrical Specifications
213
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