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SNVU704 – February 2020

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Copyright © 2020, Texas Instruments Incorporated

TLV840EVM Voltage Supervisor User Guide

User's Guide

SNVU704 – February 2020

TLV840EVM Voltage Supervisor User Guide

This user guide describes the TLV840EVM evaluation module (EVM). This guide contains the EVM
schematic, bill of materials (BOM), assembly drawing, and top and bottom board layouts.

Contents

1

Introduction

...................................................................................................................

3

1.1

Related Documentation

............................................................................................

4

1.2

TLV840 Applications

...............................................................................................

4

2

Schematic, Bill of Materials, and Layout

.................................................................................

4

2.1

TLV840EVM Schematic

............................................................................................

5

2.2

TLV840EVM Bill of Materials

......................................................................................

6

2.3

Layout and Component Placement

...............................................................................

7

3

EVM Connectors

.............................................................................................................

9

3.1

EVM Test Points

....................................................................................................

9

3.2

EVM Jumpers

.......................................................................................................

9

4

EVM Setup and Operation

...............................................................................................

10

4.1

Input Power (V

DD

)

..................................................................................................

10

4.2

Monitoring Voltage on VDD

......................................................................................

10

4.3

Reset Output (RESET)

...........................................................................................

11

4.4

Reset Time Delay Programming (Program t

D

via CT)

........................................................

11

List of Figures

1

TLV840EVM Board Top

....................................................................................................

3

2

TLV840EVM Board Bottom

.................................................................................................

4

3

TLV840EVM Schematic

....................................................................................................

5

4

Component Placement—Top Assembly

..................................................................................

7

5

Component Placement—Bottom Assembly

..............................................................................

7

6

Layout—Top

..................................................................................................................

7

7

Layout—Bottom

..............................................................................................................

7

8

Top Layer

.....................................................................................................................

7

9

Bottom Layer

.................................................................................................................

7

10

Top Solder Mask

.............................................................................................................

8

11

TLV840EVM RESET Asserted Due to MR Pulled Low

...............................................................

10

12

TLV840EVM RESET Deasserted Due to MR Pulled High, C

T

Floating

.............................................

10

13

TLV840EVM Glitch Immunity

.............................................................................................

10

14

TLV840EVM RESET Delay Time (t

D

) with C

T

Tied to GND Through 0.1-µF Capacitor

...........................

12

15

TLV840EVM RESET Delay Time (t

D

) with C

T

Tied to GND Through 0.01-µF Capacitor

.........................

12

16

TLV840EVM RESET Delay Time (t

D

) with C

T

Floating

................................................................

12

List of Tables

1

BOM

..........................................................................................................................

6

2

Test Points

....................................................................................................................

9

3

List of Onboard Jumpers

...................................................................................................

9

4

Nominal Supply and Typical Threshold Voltages

......................................................................

10

Summary of Contents for TLV840EVM

Page 1: ...peration 10 4 1 Input Power VDD 10 4 2 Monitoring Voltage on VDD 10 4 3 Reset Output RESET 11 4 4 Reset Time Delay Programming Program tD via CT 11 List of Figures 1 TLV840EVM Board Top 3 2 TLV840EVM...

Page 2: ...2 SNVU704 February 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated TLV840EVM Voltage Supervisor User Guide Trademarks All trademarks are the property of their respect...

Page 3: ...X or TLV840PHXX the shunt on J2 must be removed as push pull devices do not use a pull up resistor so R1 must be disconnected If using TLV840EVM with the active high variant TLV840PHXX the active low...

Page 4: ...Power Ultra Low Voltage Supervisor with Ajustable Reset Time Delay data sheet SBVSBC3 1 2 TLV840 Applications Motor Drives Factory Automation and Control Home Theater and Entertainment Electronic Poin...

Page 5: ...Bill of Materials and Layout 5 SNVU704 February 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated TLV840EVM Voltage Supervisor User Guide 2 1 TLV840EVM Schematic Figure...

Page 6: ...4 Bumpon Hemisphere 0 44 X 0 20 Clear Transparent Bumpon SJ 5303 CLEAR 3M J1 J2 J3 J5 J6 5 Header 100mil 2x1 TH Header 2x1 100mil TH 800 10 002 10 001000 Mill Max J4 1 Header 100mil 3x1 TH Header 3x1...

Page 7: ...t Figure 4 and Figure 5 show the top and bottom assemblies of the printed circuit board PCB to show the component placement on the EVM Figure 6 and Figure 7 show the top and bottom layouts Figure 8 an...

Page 8: ...and Layout www ti com 8 SNVU704 February 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated TLV840EVM Voltage Supervisor User Guide Figure 8 Top Layer Figure 9 Bottom Lay...

Page 9: ...o GND pin Allows user to connect to the ground plane 3 2 EVM Jumpers Table 3 lists the jumpers on the TLV840EVM As ordered the EVM will have five jumpers installed Table 3 List of Onboard Jumpers JUMP...

Page 10: ...ts to logic high Pin 1 of jumper J6 can also be connected to a control signal to set the logic level on MR pin If pin 1 on jumper J6 is logic low the device asserts a reset There is also a test point...

Page 11: ...RESET time delay connect CT pin to a capacitor to GND or leave CT pin floating The reset time delay can be set to a minimum value of 80 s by leaving the CT pin floating or a maximum value of approxim...

Page 12: ...mper on pin 2 middle pin and pin 3 right pin of jumper J4 to connect CT to delay capacitor C3 This connects the CT pin to a 0 01 F capacitor to set the RESET delay tD to 6 2 ms as shown in Figure 15 B...

Page 13: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 14: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 15: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 16: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 17: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 18: ...e resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reprod...

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