VDD
RESET
Glitch Immunity V
IT-
(t
GI_VIT-
) = 10 µs
EVM Setup and Operation
11
SNVU704 – February 2020
Copyright © 2020, Texas Instruments Incorporated
TLV840EVM Voltage Supervisor User Guide
Figure 13. TLV840EVM Glitch Immunity
4.3
Reset Output (RESET)
The TLV840EVM comes populated with TLV840MADL29 device variant which has open-drain, active-low
output topology for the RESET pin. The other device variants provide different output topolgies and can be
used on this EVM. Note: if using a TLV840 device variant with push-pull output topology, the pull-up
resistor must be disconnected by leaving jumper J2 open. The EVM provides a jumper J3 and a test point
TP3 connected directly to the RESET pin for monitoring and/or interfacing to other devices. The reset
signal will be asserted low when MR is pulled low or when the voltage on the VDD pin falls below VIT-.
When the voltage on VDD rises higher than the hysteresis voltage above the threshold voltage, and the
MR pin is pulled high or floating, the reset pins will deassert and remain deasserted until a reset condition
occurs again.
4.4
Reset Time Delay Programming (Program t
D
via CT)
The TLV840 device has two options for setting the RESET time delay: connect CT pin to a capacitor to
GND, or leave CT pin floating. The reset time delay can be set to a minimum value of 80 µs by leaving the
CT pin floating, or a maximum value of approximately 6.2 seconds by connecting 10 µF delay capacitor.
The reset time delay (t
D
) can be programmed to any value within the range by connecting a capacitor no
larger than 10 µF between CT pin and GND. The relationship between external capacitor (C
CT_EXT
) at CT
pin and the RESET time delay is given by
t
D
= -ln (0.29) x R
CT
x C
CT_EXT
+ t
D
(no cap)
(1)
is simplified to
by plugging R
CT
and T
D(no cap)
given in the Electrical Characteristics
Table in
t
D
= 618937 x C
CT_EXT
+ 80µs
(2)
solves for external capacitor value (C
CT_EXT
)
C
CT_EXT
= (t
D
- 80µs) ÷ 618937
(3)
The recommended maximum delay capacitor for the TLV840 is limited to 10 µF as this ensures there is
enough time for the capacitor to fully discharge when the reset condition occurs. When a voltage fault
occurs, the previously charged up capacitor discharges, and if the monitored voltage returns from the fault
condition before the delay capacitor discharges completely, the delay capacitor will begin charging from a
voltage above zero and the reset delay will be shorter than expected. Larger delay capacitors can be used
so long as the capacitor has enough time to fully discharge during the duration of the voltage fault.