MR
RESET
Delay from release MR to deasert reset (t
MR_tD
) = 3.5 µs
MR
RESET
Propagation delay from MR low to reset (t
MR_RES
) = 1.07 µs
EVM Setup and Operation
10
SNVU704 – February 2020
Copyright © 2020, Texas Instruments Incorporated
TLV840EVM Voltage Supervisor User Guide
4
EVM Setup and Operation
This section describes the functionality and operation of the TLV840EVM. The user must read the
datasheet for electrical characteristics of the device.
4.1
Input Power (V
DD
)
The VDD supply is connected through the J1 header on board. Both pins of jumper J1 are connected
together so power can be applied to either pin. Supply voltage is dependent on what the user wants to
monitor, but the range is 0.7 V to 6 V.
details the nominal supply and typical threshold voltage.
Table 4. Nominal Supply and Typical Threshold Voltages
Device
Nominal Supply Voltage (V)
Typical Threshold Voltage (V)
TLV840MADL13
1.3
1.3 ± 1%
4.1.1
Manual Reset (MR)
The TLV840 devices offers a manual reset pin that is utilized via jumper J6. If a shunt jumper is placed on
jumper J6, the RESET pin is asserted and forced into a low state. After the shunt jumper is removed and
VDD is above its reset threshold, MR returns to a logic high due to the internal pull-up resistor, and
RESET is deasserted to logic high after the user-defined delay expires. If jumper J6 is left floating, the
device operates normally as the MR pin defaults to logic high. Pin 1 of jumper J6 can also be connected
to a control signal to set the logic level on MR pin. If pin 1 on jumper J6 is logic low, the device asserts a
reset. There is also a test point TP4 connected directly to the MR pin in case the user wants to monitor
the MR pin. See
through
.
Figure 11. TLV840EVM RESET Asserted Due to MR
Pulled Low
Figure 12. TLV840EVM RESET Deasserted Due to MR
Pulled High, C
T
Floating
4.2
Monitoring Voltage on VDD
The TLV840 device monitors voltage via the VDD pin. The EVM provides jumper J1 and test point TP1 for
connecting the power supply input to the VDD pin. If the voltage on this pin drops below V
IT-
, RESET is
asserted low. The VDD pin is connected internally to a comparator through an internal resistor divider at
the positive input and the negative input is connected to an internal reference. The internal resistor divider
is set to provide the input voltage threshold to cause a reset, V
IT-
, that corresponds to the chosen device
variant. Please see the Device Comparison Table in the
for more information on the
different device variants.
Upon startup, the TLV840 requires VDD to be above V
DD (MIN)
= 0.7 V before the RESET output is in the
correct logic state. The TLV840 has built-in glitch immunity so voltage transients on VDD are ignored if the
pulse duration is 10 µs or less as shown in
. The glitch immunity specification depends on the
amplitude of the voltage transient and the operating conditions. Please see the Glitch Immunity
specification in the Timing Requirements section of the
for more detailed information.