SRC1_RXCXO
SRC2_MCLK
SRC1_RDYz
TAS_SCL
TAS_SDA
RESETz
SRC1_MCLK
WCLK2
BCLK2
DIN2
SRC1_LOCKz
I2S2_DOUT_SRC
SRC2_RXCXO
SRC1_MCLK
SRC2_RDYz
SRC2_MCLK
DOUT3
WCLK3
BCLK3
DIN3
SRC2_LOCKz
TAS_DIN
TAS_WCLK
TAS_BCLK
DOUT2
WCLK1
BCLK1
DOUT1
DIN1
I2S1_DOUT
I2S3_DOUT_SRC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C17
0.1uF/16V
C18
0.1uF/16V
C19
10uF/6.3V
C20
0.1uF/16V
C21
10uF/6.3V
C22
0.1uF/16V
C23
0.1uF/16V
C24
10uF/6.3V
C25
0.1uF/16V
C26
0.1uF/16V
C27
0.1uF/16V
C28
0.1uF/16V
R18
10k
R19
0
R20
0
C29
0.1uF/16V
C30
0.1uF/16V
C31
10uF/6.3V
C32
0.1uF/16V
C33
10uF/6.3V
C34
0.1uF/16V
C35
0.1uF/16V
C36
10uF/6.3V
C37
0.1uF/16V
C38
0.1uF/16V
C39
0.1uF/16V
C40
0.1uF/16V
R21
10k
R22
0
R23
0
R24
4.7k
R25
10k
R26
4.7k
C41
10uF/6.3V
C42
10uF/6.3V
1.00k
R27
1.00k
R28
GND
GND
GND
C43
0.1uF/16V
C44
0.1uF/16V
R29
10k
L;DN
11
C
C
JOHN FEDAK IV
JANUARY 31, 2014
AIP013C_Schematic.sbk
DESIGN LEAD
PAGE INFO:
FILENAME
DATE
OF
DRAWN BY
SHEET
PCB REV
SCH REV
+3.3VIO
+3.3VIO
+3.3VIO
+3.3VIO
+3.3VIO
+3.3VIO
+3.3VIO
+3.3VIO
+3.3VIO
+3.3VIO
+3.3VIO
+3.3VIO
+3.3VIO
+3.3VIO
+3.3VIO
+3.3VIO
+3.3VIO
GND
SPDIF-OUT1
2
1
3
PLT133/T10W
SHIELD
GND
INPUT
VCC
1
2
3
SPDIF-IN1
PLR135/T10
Case
GND
VCC
OUT
GND
SPDIF-IN2
3
2
1
PLR135/T10
Case
GND
VCC
OUT
GND
GND
3
1
2
SPDIF-OUT2
PLT133/T10W
SHIELD
GND
INPUT
VCC
IOVD1
+1.8VIO
IOVD2
+1.8VIO
IOVD1
+3.3VIO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TXS0104EPWR
U13
B4
NC
OE
NC
A4
B3
B2
B1
VCCB
A1
A2
A3
VCCA
14
13
12
11
10
9
8
7
6
5
4
3
2
1
U9
TXS0104EPWR
B4
NC
OE
NC
A4
B3
B2
B1
VCCB
A1
A2
A3
VCCA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
U14
TXS0104EPWR
B4
NC
OE
NC
A4
B3
B2
B1
VCCB
A1
A2
A3
VCCA
(DAC Data)
U6
Connect Pin44 to Pin10,
pin 10 to ground plane
SRC #1
SRC4392IPFBR
i2c: 1110 000
1
3
1
2
3
4
5
6
7
8
9
10
11
12
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
25
26
27
28
29
30
31
32
33
34
35
36
3
7
3
8
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
U10
Connect Pin44 to Pin10,
pin 10 to ground plane
SRC4392IPFBR
SRC #2
i2c: 1110 001
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
36
35
34
33
32
31
30
29
28
27
26
25
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
12
11
10
9
8
7
6
5
4
3
2
1
1
3
TLV320AIC3268RGC EVALUATION BOARD
3
DATA, SAMPLE RATE CONVERTER
Use same IOVD for IOVD1 and IOVD2.
BCLK3 -> GPIO2 (IOVD1)
WCLK3 -> GPIO1 (IOVD1)
DIN3 -> GPIO3 (IOVD2)
DOUT3 -> GPIO4 (IOVD2)
SAMPLE RATE CONVERTERS FOR ASIs
TI
GND
GND
GND
TLV320AIC3268EVM-U EVM Schematics
Figure 7. Sample Rate Converters for ASIs
10
TLV320AIC3268EVM-U Evaluation Module
SLAU564A – February 2014 – Revised February 2014
Copyright © 2014, Texas Instruments Incorporated