Introduction
1-2
1.1
Introduction
Low cost and design simplicity make buck converters popular solutions in dc/
dc step-down applications where lack of isolation from the input source is not
a concern. Loop compensation for the buck converter can be set for high band-
widths. This mode is desirable for the low peak-to-average current ratio, eas-
ing the component worst-case design parameters.
Figure 1–1 shows a block diagram of a typical buck converter. The converter
passes a duty-cycle modulated waveform through a low-pass output filter. To
maintain the desired output voltage, a controller senses the output voltage,
compares it to an internal reference voltage and adjusts the width of the power
switch (Q1) on time, . A commutating diode (CR1) maintains continuous
current through the inductor when the power switch is turned off.
Figure 1–1. Typical Buck Converter Block Diagram
Controller
FB
R1
R2
Q1
R3
CR1
+
C2
+
C1
V
O
V
I
L1
The SLVP097 buck converter uses the TI TL5001 PWM controller and the
TPS2817 MOSFET driver to give a 0- to 2.5-A output with a selectable output
voltage of either 3.3 V or 5 V. The converter operates over an input voltage
range of 5.5 V to 12 V with a typical efficiency of 90 percent. Chapter 2 lists full
design specifications.
Note: Peak currents in excess of 2.5 A may be obtained from this EVM,
but due to thermal restraints, should not be subtained. This EVM shuts
down when a short circuit is encountered. Input power must be re-
cycled to restart the module.
