Design Procedures
2-6
Soft-start is added to reduce power-up transients. This is implemented by
adding a capacitor across the dead-time resistor. In this design, a soft-start
time of 5 ms is used:
C
+
t
R
R
DT
+
0.005 s
47 k
W +
0.1
m
F
The TL5001 has short circuit protection (SCP) instead of a current sense cir-
cuit. If not used, the SCP terminal must be connected to ground to allow the
converter to start up. If a timing capacitor is connected to SCP, it should have
a time constant that is greater than the soft-start time constant. This time
constant is chosen to be 75 ms:
C(
m
F)
+
12.46
t
SCP
+
12.46
0.075 s
+
0.93
m
F
2.3.7
Loop Compensation
Loop compensation is necessary to stabilize the converter over the full range
of load, line, and gain conditions. A buck-mode converter has a two-pole LC
output filter with a 40-dB-per-decade rolloff. The total closed-loop response
needed for stability is a 20-dB-per-decade rolloff with a minimum phase margin
of 30 degrees over the full bandwidth for all conditions. In addition, sufficient
bandwidth must be designed into the circuit to assure that the converter has
good transient response. Both of these requirements are met by adding
compensation components around the error amplifier to modify the total loop
response.
The first step in design of the loop compensation network is the design of the
output sense divider. This sets the output voltage and the top resistor
determines the relative size of the rest of the compensation design. Since the
TL5001 input bias current is 0.5
m
A (worst case), the divider current should be
at least 0.5 mA. Using a 1-k
W
resistor for the bottom of the divider gives a
divider current of 1 mA. Since this is a dual-voltage output, the divider must be
selectable. For a 5-V output, the divider was set for 1 k
W
and 4 k
W
. The bottom
of the divider is calculated for the 3-V mode as:
R
+
R
T
V
O
*
V
REF
+
4 k
W
3.3
*
1
+
1.74 k
W
The pulse-width modulator gain can be approximated as the change in output
voltage divided by the change in PWM input voltage:
A
PWM
+
D
V
O
D
V
COMP
+
9–0
1.4–0.6
+
11.25
å
21 dB
The LC filter has a double pole at:
1
2
p
LC
Ǹ
+
1.87 kHz
and rolls off at 40-dB per decade after that until the ESR zero is reached at:
1
2
p
R
ESR
C
+
1
2
p
(0.027)
ǒ
220
10–6
Ǔ
+
26.8 kHz
