Design Procedures
2-4
2.3
Design Procedures
Detailed steps in the design of a buck-mode converter may be found in
Designing With the TL5001C PWM Controller (literature number SLVA034)
from Texas Instruments. This section shows the basic steps involved in this
design, using the 3.3-V output mode.
2.3.1
Duty Cycle Estimate
The duty cycle for a continuous-mode step-down converter is approximately:
D
+
V
O
)
V
d
V
I
*
V
SAT
Assuming the commutating diode forward voltage V
d
= 0.5 V and the power
switch on voltage V
SAT
= 0.1 V, the duty cycle for V
i
= 5.5, 9, and 12 V is 0.70,
0.42, and 0.32, respectively.
2.3.2
Output Filter
A buck converter uses a single-stage LC filter. Choose an inductor to maintain
continuous-mode operation down to 6 percent of the rated output load:
D
I
O
+
2
0.06
I
O
+
2
0.06
2.5
+
0.30 A
The inductor value is:
L
+
(V
I
*
V
SAT
*
V
O
)
D
t
D
I
O
+
(12
*
0.1
*
3.3)
0.32
ǒ
3.63
10–6
Ǔ
0.30
+
33.3
m
H
Assuming that all of the inductor ripple current flows through the capacitor and
the effective series resistance (ESR) is zero, the capacitance needed is:
C
+
D
I
O
8
f
ǒ
D
V
O
Ǔ
+
0.3
8
ǒ
275
103
Ǔ
0.05
+
2.73
m
F
Assuming the capacitance is very large, the ESR needed to limit the ripple to
50 mV is:
ESR
+
D
V
O
D
I
O
+
0.05
0.3
+
0.167
W
The output filter capacitor should be rated at least ten times the calculated
capacitance and 30–50 percent lower than the calculated ESR. This design
used a 220-
m
F OS-Con capacitor in parallel with a ceramic to reduce ESR.
2.3.3
Power Switch
Based on the preliminary estimate, r
DS(ON)
should be less than 0.10 V
2.5 A
= 40 m
W
. The IRF7406 is a 30-V p-channel MOSFET with r
DS(ON)
= 40 m
W.
Power dissipation (cond switching losses) can be estimated as:
P
D
+
ǒ
I2
O
r
DS(ON)
D
Ǔ
)
ǒ
0.5
V
i
I
O
t
r
)
f
f
Ǔ
