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S
F
R
b
u
s
S
F
R
b
u
s
MEMORY
ARBITRATOR
8051 CPU
CORE
DMA
FLASH
SRAM
FLASH CTRL
DEBUG
INTERFACE
RESET
RESET_N
P2_4
P2_3
P2_2
P2_1
P2_0
P1_4
P1_3
P1_2
P1_1
P1_0
P1_7
P1_6
P1_5
P0_4
P0_3
P0_2
P0_1
P0_0
P0_7
P0_6
P0_5
32.768 kHz
CRYSTAL OSC
32 MHz
CRYSTAL OSC
HIGH SPEED
RC-OSC
32 kHz
RC-OSC
CLOCK MUX &
CALIBRATION
RAM
USART 0
USART 1
TIMER 1 (16-bit)
TIMER 3 (8-bit)
TIMER 2
(BLE LL TIMER)
TIMER 4 (8-bit)
AES
ENCRYPTION
&
DECRYPTION
WATCHDOG TIMER
IRQ
CTRL
FLASH
UNIFIED
RF_P RF_N
S
Y
N
T
H
MODULATOR
POWER ON RESET
BROWN OUT
RADIO
REGISTERS
POWER MGT. CONTROLLER
SLEEP TIMER
PDATA
XRAM
IRAM
SFR
XOSC_Q2
XOSC_Q1
DS
ADC
AUDIO / DC
DIGITAL
ANALOG
MIXED
VDD (2.0 - 3.6 V)
DCOUPL
ON-CHIP VOLTAGE
REGULATOR
Link Layer Engine
F
R
E
Q
U
E
N
C
Y
S
Y
N
T
H
E
S
IZ
E
R
I2C
DEMODULATOR
RECEIVE
TRANSMIT
OP-AMP
ANALOG COMPARATOR
I/
O
C
O
N
T
R
O
L
L
E
R
1 KB SRAM
R
a
d
io
A
rb
it
e
r
FIFOCTRL
SDA
SCL
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Block Diagram
2.1.2
CC2541
Figure 3. CC2541 Block Diagram
5
TIDU195A – January 2014 – Revised July 2014
Wireless Heart Rate Monitor Reference Design
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