Stellaris® LM3S9B96 Development Kit User’s Manual
September 5, 2010
63
EPI Signal Descriptions
Table F-8 provides the EPI module’s signal descriptions.
Table F-8. EPI Signal Descriptions
EPI Signal
Port
FPGA Signal
Direction
Description
EPIOS[31]
PG7
CLK
In
EPI Clock
EPIOS[30]
PJ6
E_IRQn
Out
Interrupt Signal to Microcontroller
a
a.
Configure as Stellaris GPIO input with negative level sensitive interrupts. During power up/reset is used for PLL lock status.
EPIOS[29]
PJ5
E_RD
In
EPI Read Strobe
EPIOS[28]
PJ4
E_WR
In
EPI Write Strobe
EPIOS[27]
PH7
E_RDY
Out
EPI Ready Signal
EPIOS[26]
PH6
E_RSTn
In
FPGA Reset Signal
b
b.
Configure as Stellaris GPIO output.
EPIOS[25:16]
PE3,PE2,PB4,
PB5,PD3,PD2,PJ3,
PJ2,PJ1,PJ0
E_ADDR[10:1]
In
EPI Address Bus
EPIOS[15:0]
PF5,PG1,PG0,PF4,
PH5,PH4,PE1,PE0,
PH1,PH0,PC7,PC6,
PC5,PC4,PH2,PH3
E_DATA[15:0]
I/O
EPI Data Bus
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