Texas Instruments SM320C6455-EP Data Manual Download

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SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR

Data Manual

JANUARY 2008

SPRS462B

Summary of Contents for SM320C6455-EP

Page 1: ...SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR Data Manual JANUARY 2008 SPRS462B...

Page 2: ...er SPRS462B SEPTEMBER 2007 Revised JANUARY 2008 PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of the Texas Instruments standard warrant...

Page 3: ...tate Control Registers 65 3 4 1 Peripheral Lock Register Description 66 3 4 2 Peripheral Configuration Register 0 Description 67 3 4 3 Peripheral Configuration Register 1 Description 69 3 4 4 Peripher...

Page 4: ...R Pin 128 7 6 2 Warm Reset RESET Pin 129 7 6 3 Max Reset 130 7 6 4 System Reset 130 7 6 5 CPU Reset 130 7 6 6 Reset Priority 131 7 6 7 Reset Controller Register 132 7 6 7 1 Reset Type Status Register...

Page 5: ...ral Register Description s 175 7 11 3 I2C Electrical Data Timing 176 7 11 3 1 Inter Integrated Circuits I2C Timing 176 7 12 Host Port Interface HPI Peripheral 179 7 12 1 HPI Device Specific Informatio...

Page 6: ...7 20 Serial RapidIO SRIO Port 234 7 20 1 Serial RapidIO Device Specific Information 234 7 20 2 Serial RapidIO Peripheral Register Description s 234 7 20 3 Serial RapidIO Electrical Data Timing 244 7 2...

Page 7: ...on 2 3 16M Bit 2096K Byte L2 Unified Mapped RAM Cache Flexible Allocation One Inter Integrated Circuit I2 C Bus 256K Bit 32K Byte L2 ROM Two McBSPs Time Stamp Counter 10 100 1000 Mb s Ethernet MAC EMA...

Page 8: ...1 JTAG Figure 1 1 shows the SM320C6455 EP device 697 pin ball grid array package bottom view Figure 1 1 ZTZ GTZ BGA Package Bottom View The C64x DSPs including the SM320C6455 EP device are the highes...

Page 9: ...s a user configurable 16 bit or 32 bit host port interface HPI16 HPI32 a peripheral component interconnect PCI a 16 pin general purpose input output port GPIO with programmable interrupt event generat...

Page 10: ...D EMAC 10 100 1000 SPLOOP Buffer Power Control L1D Memory Controller Memory Protect Bandwidth Mgmt Interrupt and Exception Controller EDMA 3 0 L2 ROM 32K Bytes E Secondary Switched Central Resource A...

Page 11: ...y General Purpose Input Output Port GPIO 16 VCP2 clock source CPU 3 clock frequency 1 Decoder Coprocessors TCP2 clock source CPU 3 clock frequency 1 Size Bytes 2192K 32K Byte 32KB L1 Program Memory Co...

Page 12: ...4x CPU extends the performance of the C64x core through enhancements and new features Each C64x M unit can perform one of the following each clock cycle one 32 x 32 bit multiply two 16 x 16 bit multip...

Page 13: ...Handling Intended to aid the programmer in isolating bugs The C64x CPU is able to detect and respond to exceptions both from internally detected sources such as illegal op codes and from system events...

Page 14: ...2 MSB 32 LSB dst2 A 32 MSB 32 LSB 2x 1x 32 LSB 32 MSB 32 LSB 32 MSB dst2 B B A 8 8 8 8 32 32 32 32 C C Even register file A A0 A2 A4 A30 Even register file B B0 B2 B4 B30 D D D D A On M unit dst2 is 3...

Page 15: ...FFFF Timer 1 Registers 128K 0298 0000 0299 FFFF PLL1 Controller including Reset Controller Registers 512 029A 0000 029A 01FF Reserved 256K 512 029A 0200 029B FFFF PLL2 Controller Registers 512 029C 0...

Page 16: ...00 0400 3C00 07FF Reserved 16M 2K 3C00 0800 3CFF FFFF Reserved 48M 3D00 0000 3FFF FFFF PCI External Memory Space 256M 4000 0000 4FFF FFFF TCP2 Data Registers 128M 5000 0000 57FF FFFF VCP2 Data Registe...

Page 17: ...11b If host boot is selected after reset the CPU is internally stalled while the remainder of the device is released During this period an external host can initialize the CPU s memory space as necess...

Page 18: ...evice acting as an I2C slave to the DSP using a predefined boot table format The destination address and length are contained within the boot table This boot mode is a software boot mode Slave I2C boo...

Page 19: ...boot modes can be used to download a 2nd level bootloader A 2nd level bootloader allows for any level of customization to current boot methods as well as definition of a completely customized boot TI...

Page 20: ...VDD33 VSS VSS HD19 AD19 HD13 AD13 HD29 AD29 DVDD33 DVDD33 HD25 AD25 DVDD33 HD0 AD0 VSS HD11 AD11 TOUTL0 EMU3 EMU7 TOUTL1 VSS DVDD33 VSS DVDD33 VSS HDS2 PCBE1 HCNTL0 PSTOP HCS PPERR VSS HD8 AD8 VSS HD2...

Page 21: ...DVDD12 AED24 DVDD33 VSS VSS AED19 DVDD33 CVDD CVDD DVDD33 VSS VSS DVDD33 DVDD33 VSS VSS VSS DVDD33 VSS AED26 VSS DVDD33 AED22 AED0 AED13 AED12 AED10 RIOTX0 AVDDT RIOTX3 AED30 DVDD33 AEA12 UTOPIA_EN VS...

Page 22: ...DSDDQ GATE3 RSV19 AED55 VSS DVDD18 DVDD18 AED39 DVDD33 VSS VSS RSV30 DVDD33 VSS VSS DVDD18 VSS DVDD18 DVDD18 AED35 AED48 AED54 DVDD18 VSS DVDD33 AED47 DVDD33 DVDD33 AED57 DED27 DSDDQS2 DEA0 AED41 DSDD...

Page 23: ...VDD15 DED12 DVDD18 DED5 RGRXD0 DVDD33 VSS VSS VSS DVDD33MON VSS RSV21 DED13 DED4 VSS AVDLL1 VSS VREFHSTL RGMDCLK RSV24 DSDDQ GATE1 RGRXCTL VSS DVDD15 RGTXC RGRXC DSDDQS1 DVDD18 DVDD18 RSV14 DVDD18 URD...

Page 24: ...U15 EMU16 EMU17 RSV02 EMU18 RSV07 RSV09 RSV05 RSV43 RSV44 RSV42 RESETSTAT CLKIN2 POR PCI_EN Peripheral Enable Disable Clock PLL2 PLLV2 PLLV1 A This pin functions as GP 1 by default For more details se...

Page 25: ...re details see the Device Configuration section of this document GPIO General Purpose Input Output 0 GPIO Port CLKX1 GP 3 B URADDR4 PCBE0 GP 2 C SYSCLK4 GP 1 A URADDR3 PREQ GP 15 C URADDR2 PINTA GP 14...

Page 26: ...DDR2 Memoty Controller 32 bit Data Bus DSDCAS DSDCKE DDR2CLKOUT DSDDQS 3 0 DSDRAS DSDWE DSDDQS 3 0 ABE7 ABE6 ABE5 ABE4 ACE5 A Bank Address ABA 1 0 AR W AAOE ASOE ASADS ASRE Bank Address DBA 2 0 DEODT...

Page 27: ...are muxed with the PCI peripheral By default these pins function as HPI When the HPI is enabled the number of HPI pins used depends on the HPI configuration HPI16 or HPI32 For more details on these m...

Page 28: ...details on these muxed pins see the Device Configuration section of this document RGTXC RGRXC RGREFCLK UXDATA 7 2 MTXD 7 2 UXDATA 1 0 MTXD 1 0 RMTXD 1 0 Transmit RGMII A GMII RMII MII RGRXD 3 0 URDATA...

Page 29: ...PIO or EMAC peripheral pins or have no function For more details on these muxed pins see the Device Configuration section of this data sheet HD 15 0 AD 15 0 HR W PCBE2 HDS2 PCBE1 UXADDR4 PCBE0 GP 2 HH...

Page 30: ...e the IEEE TRST AH7 I IPD 1149 1 JTAG compatibility statement portion of this document EMU0 4 AF7 I O Z IPU Emulation pin 0 EMU1 4 AE11 I O Z IPU Emulation pin 1 EMU2 AG9 I O Z IPU Emulation pin 2 EMU...

Page 31: ...IPD or this pin can be programmed as a GP 1 pin I O Z default URADDR4 PCBE0 P1 I O Z GP 2 SYSCLK4 GP 1 AJ13 O Z IPD CLKR1 GP 0 AF4 I O Z IPD HOST PORT INTERFACE HPI or PERIPHERAL COMPONENT INTERCONNEC...

Page 32: ...O Z I O Z By default this pin has no function UTOPIA transmit address pin 1 UXADDR1 I or PCI initialization device UXADDR1 PIDSEL R3 I select I By default this pin has no function UTOPIA transmit addr...

Page 33: ...number of address bits or byte enables used depends on the width of external memory ABE3 AA29 O Z IPU Byte write enables for most types of memory ABE2 AA28 O Z IPU ABE1 AA25 O Z IPU ABE0 AA26 O Z IPU...

Page 34: ...rations For more detailed information on the boot modes see Section 2 4 Boot Sequence CFGGP 2 0 pins must be set to 000b during reset for proper operation of the PCI boot mode EMIFA input clock source...

Page 35: ...zation through I2C EEPROM is enabled PCI Frequency Selection PCI66 The PCI peripheral needs be enabled PCI_EN 1 to use this function Selects the PCI operating frequency of 66 MHz or 33 MHz PCI operati...

Page 36: ...AED58 D28 AED57 D27 AED56 F27 AED55 G25 AED54 G26 AED53 A28 AED52 F28 AED51 B28 AED50 G27 AED49 B27 AED48 G28 AED47 H25 AED46 J26 AED45 H26 AED44 J27 AED43 H27 I O Z IPU EMIFA external data AED42 J28...

Page 37: ...R2 Memory Controller SDRAM column address strobe DSDRAS C13 O Z DDR2 Memory Controller SDRAM row address strobe DSDWE B13 O Z DDR2 Memory Controller SDRAM write enable DSDCKE D14 O Z DDR2 Memory Contr...

Page 38: ...O Z DDR2 data strobe 3 0 negative DSDDQS2 D20 I O Z Note These pins are used to meet AC timings For more detailed information DSDDQS1 D8 I O Z see the Implementing DDR2 PCB Layout on the TMS320C6455 a...

Page 39: ...14 D7 DED13 A7 DED12 B7 DED11 F9 DED10 E9 DED9 D9 DED8 C9 DED7 D10 DED6 C10 DED5 B10 DED4 A10 DED3 D12 DED2 C12 DED1 B12 DED0 A12 TIMER 1 TOUTL1 AG7 O Z IPD Timer 1 output pin for lower 32 bit counter...

Page 40: ...iled information see Section 3 Device Configuration Transmit cell available status output signal from UTOPIA Slave 0 indicates a complete cell is NOT available for transmit UXCLAV GMTCLK K5 I O Z 1 in...

Page 41: ...al in the next clock cycle or thereafter When the UTOPIA peripheral is disabled UTOPIA_EN AEA12 pin 0 this pin is EMAC MII default or GMII receive data valid MACSEL 1 0 dependent Receive Start of Cell...

Page 42: ...AEA12 driven low UTOPIA_EN 0 there are two additional configuration pins the MAC_SEL 1 0 AEA 10 9 pins that select one of the four interface modes MII RMII GMII or RGMII for the EMAC MDIO interface F...

Page 43: ...t or GMII transmit clock MTCLK I or the N4 I RMREFCLK EMAC RMII reference clock RMREFCLK I The EMAC function is controlled by the MACSEL 1 0 AEA 10 9 pins For more detailed information see Section 3 D...

Page 44: ...ve data 3 0 I This pin is available only when RGMII mode is selected MACSEL 1 0 11 RGRXD1 E2 I RGRXD0 E1 I RGMII receive control I This pin is available only when RGMII mode is RGRXCTL C2 I selected M...

Page 45: ...n must be connected via a 39 resistor directly to ground RSV15 T1 VSS for proper device operation The resistor used should have a minimal rating of 1 10 W Reserved This pin must be connected via a 20...

Page 46: ...RGMII pins of the EMAC To preserve boundary scan functionality on the RGMII pins see Section 7 3 4 Die side 1 8 V I O supply DVDD18 voltage monitor pin The monitor pins indicate the voltage on the die...

Page 47: ...AE17 AE19 SRIO termination supply AE23 1 25 V I O supply voltage 1000 and 1200 devices AVDDT AF20 A 1 2 V I O supply voltage 850 and 720 devices Do not use core supply AH20 NOTE If RapidIO is not used...

Page 48: ...minal Functions continued SIGNAL TYPE 1 IPD IPU 2 DESCRIPTION NAME NO A29 E26 E28 G2 H23 H28 J6 J24 K1 K7 K23 L24 M7 M23 M28 N24 P6 P28 R1 R6 R23 DVDD33 T7 S 3 3 V I O supply voltage T24 U23 V1 V7 V24...

Page 49: ...NAME NO AD5 AD7 AD14 AD18 AD22 AD24 AE6 AE8 AE15 AF1 AF16 DVDD33 AF24 S 3 3 V I O supply voltage AG12 AG17 AG23 AH14 AH16 AH24 AJ1 AJ7 AJ15 AJ25 AJ29 L12 L14 L16 L18 M11 M13 M15 M17 M19 N12 1 25 V co...

Page 50: ...AL TYPE 1 IPD IPU 2 DESCRIPTION NAME NO R18 T11 T13 T15 T17 T19 U12 1 25 V core supply voltage 1000 and 1200 devices CVDD S 1 2 V core supply voltage 850 and 720 devices U14 U18 V11 V13 V19 W12 W14 GR...

Page 51: ...VISED JANUARY 2008 Table 2 3 Terminal Functions continued SIGNAL TYPE 1 IPD IPU 2 DESCRIPTION NAME NO F20 F22 F24 G1 G5 G7 G9 G11 G13 G15 G17 G19 G21 G23 H6 H24 VSS GND Ground pins H29 J7 J23 K2 K6 K2...

Page 52: ...JANUARY 2008 Table 2 3 Terminal Functions continued SIGNAL TYPE 1 IPD IPU 2 DESCRIPTION NAME NO M16 M18 M24 M26 M29 N2 N13 N15 N17 N19 N23 P7 P12 P14 P16 P18 P29 VSS GND Ground pins R2 R7 R11 R13 R15...

Page 53: ...ANUARY 2008 Table 2 3 Terminal Functions continued SIGNAL TYPE 1 IPD IPU 2 DESCRIPTION NAME NO U15 U17 U19 U24 V2 V6 V12 V14 V16 V18 V23 W7 W11 W13 W15 W17 VSS GND Ground pins W19 W24 Y6 Y23 AA2 AA7 A...

Page 54: ...Terminal Functions continued SIGNAL TYPE 1 IPD IPU 2 DESCRIPTION NAME NO AC20 AC22 AC24 AC28 AD6 AD13 AD15 AD17 AD19 AD21 AD23 AE4 AE7 AE16 AE18 AE20 AE22 AE24 VSS GND Ground pins AF2 AF19 AF21 AG13...

Page 55: ...mily member has one of three prefixes TMX TMP or TMS e g TMS320C6455ZTZ Texas Instruments recommends two of three possible prefix designators for its support tools TMDX and TMDS These prefixes represe...

Page 56: ...6455 related peripherals and other technical collateral is available in the C6000 DSP product folder at www ti com c6000 SPRU732 TMS320C64x C64x DSP CPU and Instruction Set Reference Guide Describes t...

Page 57: ...20C645x DSP Inter Integrated Circuit I2C Module User s Guide This document describes the inter integrated circuit I2C module in the C645x Digital Signal Processor DSP The I2C provides an interface bet...

Page 58: ...2 TMS320C645x DSP Viterbi Decoder Coprocessor VCP User s Guide Channel decoding of voice and low bit rate data channels found in third generation 3G cellular standards requires decoding of convolution...

Page 59: ...upon TI recommends the use of an external pullup pulldown resistor For more detailed information on pullup pulldown resistors and situations where external pullup pulldown resistors are required see...

Page 60: ...ns select the interface used by the EMAC MDIO peripheral 00 10 100 EMAC MDIO with MII Interface default 01 10 100 EMAC MDIO with RMII Interface 10 10 100 1000 EMAC MDIO with GMII Interface M25 AEA 10...

Page 61: ...sabled default 1 EMIFA peripheral pins are enabled Some C6455 peripherals share the same pins internally multiplexed and are mutually exclusive Therefore not all peripherals may be used at the same ti...

Page 62: ...1 0 configuration pins AEA 10 9 control which interface is used by the EMAC MDIO Note that since the PCI shares some pins with the UTOPIA peripheral its state also affects the operation of the UTOPIA...

Page 63: ...abled off Default state for all peripherals not in EMAC MDIO static powerdown mode McBSP0 McBSP1 HPI PCI UTOPIA TCP VCP I2C Timer 0 Timer 1 GPIO MDIO Clock to the peripheral is turned on and the Enabl...

Page 64: ...6455 device Figure 3 2 Peripheral State Change Flow A 32 bit key value 0x0F0A 0B00 must be written to the Peripheral Lock register PERLOCK in order to allow access to the PERCFG0 register Writes to th...

Page 65: ...e Control Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02AC 0000 Reserved 02AC 0004 PERLOCK Peripheral Lock Register 02AC 0008 PERCFG0 Peripheral Configuration Register 0 02AC 000C Reserved 02AC...

Page 66: ...d from external memory If the instructions are in different fetch packets fetching the second instruction from external memory may stall the instruction long enough such that PERCFG0 register will be...

Page 67: ...ved TIMER1CTL R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 Reserved TIMER0CTL Reserved EMACCTL Reserved VCPCTL Reserved TCPCTL R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND...

Page 68: ...mode 11 Reserved Reserved 10 GPIOCTL Mode control for GPIO 0 Set GPIO to disabled mode 1 Set GPIO to enabled mode 9 Reserved Reserved 8 TIMER1CTL Mode control for Timer 1 0 Set Timer 1 to disabled mod...

Page 69: ...h the device configuration pins DDR2 EN ABA0 and EMIFA ABA1 they cannot be enabled through the PERCFG1 register 31 8 Reserved R 0x00 7 2 1 0 Reserved DDR2CTL EMIFACTL R 0x00 R W 0 R W 0 LEGEND R W Rea...

Page 70: ...on 31 30 Reserved Reserved 29 27 HPISTAT HPI status 000 HPI is in the disabled state 001 HPI is in the enabled state 011 HPI is in the static powerdown state 101 HPI is in the enable in progress state...

Page 71: ...r0 status 000 Timer0 is in the disabled state 001 Timer0 is in the enabled state 011 Timer0 is in the static powerdown state 101 Timer0 is in the enable in progress state Others Reserved 8 6 EMACSTAT...

Page 72: ...TAT1 Field Descriptions Bit Field Value Description 31 6 Reserved Reserved 5 3 UTOPIASTAT UTOPIA status 000 UTOPIA is in the disabled state 001 UTOPIA is in the enabled state 011 UTOPIA is in the stat...

Page 73: ...ved RMII_RST Reserved R W 0001b R W 1 R W 0 15 0 Reserved R W 0 LEGEND R W Read Write R Read only n value after reset Figure 3 8 EMAC Configuration Register EMACCFG 0x02AC 0020 Table 3 11 EMAC Configu...

Page 74: ...fers can be powered down if the device trace feature is not needed 31 8 Reserved R 0 7 1 0 Reserved EMUCTL R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Figure 3 9 Emulator Buffer Po...

Page 75: ...the DEVSTAT register are latched from device configuration pins as described in Section 3 1 Device Configuration at Device Reset The default values shown here correspond to the setting dictated by th...

Page 76: ...nal I2C EEPROM provided the PCI peripheral pin is enabled PCI_EN 1 10 9 MACSEL 1 0 EMAC Interface Select MACSEL 1 0 status bits Shows which EMAC interface mode has been selected 00 10 100 EMAC MDIO wi...

Page 77: ...customer the JTAG Device ID For the C6455 device the JTAG ID register resides at address location 0x02A8 0008 For the actual register bit names and their associated bit field descriptions see Figure...

Page 78: ...r a pulldown resistor this should be below the lowest VIL level of all inputs connected to the net For a pullup resistor this should be above the highest VIH level of all inputs on the net A reasonabl...

Page 79: ...2 bit Operation AEA 13 LENDIAN IPU Little Endian Mode default AEA 12 UTOPIA_EN 0 UTOPIA disabled default AEA 11 1 must oppose IPD AEA 8 PCI_EEAI 0 PCI I2C EEPROM Auto Init disabled default AEA 7 0 do...

Page 80: ...e Endian Mode default AEA 12 UTOPIA_EN 0 UTOPIA disabled default AEA 11 1 must oppose IPD AEA 8 PCI_EEAI 0 PCI I2C EEPROM Auto Init disabled default AEA 7 0 do not oppose IPD AEA 6 PCI66 0 PCI 33 MHz...

Page 81: ...s on the other hand rely on the EDMA3 to perform transfers to and from them Masters include the EDMA3 traffic controllers SRIO and PCI Slaves include the McBSP UTOPIA and I2C The C6455 device contains...

Page 82: ...requency divided by 3 Some peripherals like PCI and the C64x Megamodule have both slave and master ports Note that each EDMA3 transfer controller has an independent connection to the data SCR The Seri...

Page 83: ...SYSCLK2 128 SYSCLK2 32 SYSCLK3 32 SYSCLK3 32 SYSCLK3 32 SYSCLK3 128 SYSCLK2 128 SYSCLK2 128 SYSCLK2 32 SYSCLK3 128 SYSCLK2 64 SYSCLK2 64 SYSCLK2 Bridge Bridge Bridge 128 SYSCLK3 Bridge Bridge 128 SYS...

Page 84: ...connection between the C64x Megamodule and the configuration switched central resource SCR The configuration SCR is mainly used by the C64x Megamodule to access peripheral registers The data SCR also...

Page 85: ...K2 32 SYSCLK2 32 SYSCLK3 32 SYSCLK2 32 SYSCLK2 32 bit SYSCLK2 Configuration Bus Data Bus MUX MUX 32 SYSCLK2 32 SYSCLK2 32 SYSCLK2 32 SYSCLK2 A Only accessible by the C64x Megamodule B All clocks in th...

Page 86: ...R side when a master through the data SCR tries to access the same endpoint as the C64x megamodule In the PRI_ALLOC register the HOST field applies to the priority of the HPI and PCI peripherals The E...

Page 87: ...SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 The C64x Megamodule consists of several components the C64x CPU the L1 program and data memory controllers the L2 memory controller the i...

Page 88: ...8 Region 1 size is 32K bytes with no wait states L1D is a two way set associative cache while L1P is a direct mapped cache The L1P and L1D cache can be reconfigured via software through the L1PMODE fi...

Page 89: ...L2 memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register L2CFG of the C64x Megamodule Figure 5 4 shows the available SRAM cache configurations for...

Page 90: ...1 Table 5 1 Available Memory Page Protection Schemes AID0 Bit LOCAL Bit Description 0 0 No access to memory page is permitted 0 1 Only direct access by CPU is permitted 1 0 Only accesses by system mas...

Page 91: ...his time More information on the power down features of the C64x Megamodule can be found in the TMS320C64x Megamodule Reference Guide literature number SPRU871 Table 5 2 shows the reset types supporte...

Page 92: ...e after reset A The C64x Megamodule revision is dependant on the silicon revision being used For more information see the TMS320C6455 Digital Signal Processor Silicon Errata literature number SPRZ234...

Page 93: ...served 0180 00A0 MEVTFLAG0 Masked Event Flag Status Register 0 Events 31 0 0180 00A4 MEVTFLAG1 Masked Event Flag Status Register 1 0180 00A8 MEVTFLAG2 Masked Event Flag Status Register 2 0180 00AC MEV...

Page 94: ...MM_REVID Megamodule Revision ID Register 0181 2004 0181 2FFF Reserved Table 5 7 Megamodule IDMA Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0182 0000 IDMA0STAT IDMA Channel 0 Status Register 01...

Page 95: ...ack and Invalidate Base Address Register 0184 4034 L1DWIWC L1D Writeback and Invalidate Word Count Register 0184 4038 Reserved 0184 4040 L1DWBAR L1D Writeback Base Address Register for Block Writeback...

Page 96: ...ange BA00 0000 BAFF FFFF 0184 82EC MAR187 Controls EMIFA CE3 Range BB00 0000 BBFF FFFF 0184 82F0 MAR188 Controls EMIFA CE3 Range BC00 0000 BCFF FFFF 0184 82F4 MAR189 Controls EMIFA CE3 Range BD00 0000...

Page 97: ...000 E7FF FFFF 0184 83A0 MAR232 Controls DDR2 CE0 Range E800 0000 E8FF FFFF 0184 83A4 MAR233 Controls DDR2 CE0 Range E900 0000 E9FF FFFF 0184 83A8 MAR234 Controls DDR2 CE0 Range EA00 0000 EAFF FFFF 018...

Page 98: ...e attribute register 24 0184 A264 L2MPPA25 L2 memory protection page attribute register 25 0184 A268 L2MPPA26 L2 memory protection page attribute register 26 0184 A26C L2MPPA27 L2 memory protection pa...

Page 99: ...ry protection lock key bits 63 32 0184 AD08 L1DMPLK2 L1D memory protection lock key bits 95 64 0184 AD0C L1DMPLK3 L1D memory protection lock key bits 127 96 0184 AD10 L1DMPLKCMD L1D memory protection...

Page 100: ...lave DMA Arbitration Control Register 0184 104C L1DUCARBD L1D User Coherence Arbitration Control Register Table 5 11 Device Configuration Registers Chip Level Registers HEX ADDRESS RANGE ACRONYM REGIS...

Page 101: ...mum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended oper...

Page 102: ...VIL Low level input voltage I2C pins 0 0 3DVDD33 V RGMII pins 0 3 VREFHSTL 0 1 V DDR2 memory controller pins 0 3 VREFSSTL 0 125 V DC Maximum voltage during overshoot undershoot VOS 3 5 7 1 V PCI capab...

Page 103: ...internal pulldown resistor I2C pins 0 1DVDD33 VI 0 9DVDD33 10 10 A PCI capable pins 4 1000 1000 A RGMII pins 0 4 V AECLKOUT CLKR1 GP 0 CLKX1 GP 3 8 mA SYSCLK4 GP 1 EMU 18 0 CLKR0 CLKX0 EMIF pins excep...

Page 104: ...uency 720 MHz DVDD33 3 3 V DVDD18 DVDDR 1 8 V PLLV1 PLLV2 AVDLL1 0 54 W AVDLL2 1 8 V CPU frequency 1200 MHz DVDD33 3 3 V DVDD18 DVDDR 1 8 V PLLV1 PLLV2 AVDLL1 0 54 W AVDLL2 1 8 V CPU frequency 1000 MH...

Page 105: ...Transition Levels Vref 1 5 V Vref VIL MAX or VOL MAX Vref VIH MIN or VOH MIN 7 1 2 3 3 V Signal Transition Rates SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JAN...

Page 106: ...fers may be used to compensate any timing differences For inputs timing is most impacted by the round trip propagation delay from the DSP to the external device and from the external device to the DSP...

Page 107: ...e Physically smaller caps are better such as 0402 but need to be evaluated from a yield manufacturing point of view Parasitic inductance limits the effectiveness of the decoupling capacitors therefore...

Page 108: ...RGMII pins of the EMAC To preserve boundary scan functionality on the RGMII pins DVDD15 VREFHSTL RSV14 and RSV13 should be connected as follows DVDD15 and DVDD15MON connect these pins to the 1 8 V I O...

Page 109: ...multiple transfers to execute with one event 256 PaRAM entries Used to define transfer context for channels Each PaRAM entry can be used as a DMA entry QDMA entry or link entry 64 DMA channels Manual...

Page 110: ...nts generated by system peripherals Table 7 3 lists the source of the synchronization event associated with each of the DMA channels On the C6455 the association of each synchronization event and DMA...

Page 111: ...1 0101 GPINT5 GPIO event 5 54 011 0110 GPINT6 GPIO event 6 55 011 0111 GPINT7 GPIO event 7 56 011 1000 GPINT8 GPIO event 8 57 011 1001 GPINT9 GPIO event 9 58 011 1010 GPINT10 GPIO event 10 59 011 1011...

Page 112: ...annel 28 Mapping Register 02A0 0174 DCHMAP29 DMA Channel 29 Mapping Register 02A0 0178 DCHMAP30 DMA Channel 30 Mapping Register 02A0 017C DCHMAP31 DMA Channel 31 Mapping Register 02A0 0180 DCHMAP32 DM...

Page 113: ...0 0258 DMAQNUM6 DMA Queue Number Register 6 02A0 025C DMAQNUM7 DMA Queue Number Register 7 02A0 0260 QDMAQNUM QDMA Queue Number Register 02A0 0264 02A0 0280 Reserved 02A0 0284 QUEPRI Queue Priority Re...

Page 114: ...ueue 0 Entry Register 7 02A0 0420 Q0E8 Event Queue 0 Entry Register 8 02A0 0424 Q0E9 Event Queue 0 Entry Register 9 02A0 0428 Q0E10 Event Queue 0 Entry Register 10 02A0 042C Q0E11 Event Queue 0 Entry...

Page 115: ...gister 7 02A0 04E0 Q3E8 Event Queue 3 Entry Register 8 02A0 04E4 Q3E9 Event Queue 3 Entry Register 9 02A0 04E8 Q3E10 Event Queue 3 Entry Register 10 02A0 04EC Q3E11 Event Queue 3 Entry Register 11 02A...

Page 116: ...econdary Event Register 02A0 103C SERH Secondary Event Register High 02A0 1040 SECR Secondary Event Clear Register 02A0 1044 SECRH Secondary Event Clear Register High 02A0 1048 02A0 104C Reserved 02A0...

Page 117: ...r Register High 02A0 2060 IESR Interrupt Enable Set Register 02A0 2064 IESRH Interrupt Enable Set Register High 02A0 2068 IPR Interrupt Pending Register 02A0 206C IPRH Interrupt Pending Register High...

Page 118: ...dentification Register 02A2 0004 TCCFG EDMA3TC Configuration Register 02A2 0008 02A2 00FC Reserved 02A2 0100 TCSTAT EDMA3TC Channel Status Register 02A2 0104 02A2 011C Reserved 02A2 0120 ERRSTAT Error...

Page 119: ...ns Register 2 02A2 0384 DFSRC2 Destination FIFO Source Address Register 2 02A2 0388 DFCNT2 Destination FIFO Count Register 2 02A2 038C DFDST2 Destination FIFO Destination Address Register 2 02A2 0390...

Page 120: ...Y0 Destination FIFO Memory Protection Proxy Register 0 02A2 8318 02A2 833C Reserved 02A2 8340 DFOPT1 Destination FIFO Options Register 1 02A2 8344 DFSRC1 Destination FIFO Source Address Register 1 02A...

Page 121: ...FO Set Destination Address B Reference Register 02A3 0288 DFDSTBREF Destination FIFO Set Destination Address B Reference Register 02A3 028C 02A3 02FC Reserved 02A3 0300 DFOPT0 Destination FIFO Options...

Page 122: ...egister 02A3 8248 SACNT Source Active Count Register 02A3 824C SADST Source Active Destination Address Register 02A3 8250 SABIDX Source Active Source B Index Register 02A3 8254 SAMPPRXY Source Active...

Page 123: ...ount Register 2 02A3 838C DFDST2 Destination FIFO Destination Address Register 2 02A3 8390 DFBIDX2 Destination FIFO BIDX Register 2 02A3 8394 DFMPPRXY2 Destination FIFO Memory Protection Proxy Registe...

Page 124: ...re not connected and therefore 4 8 Reserved not used EMU interrupt for 1 Host scan access 9 1 EMU_DTDMA 2 DTDMA transfer complete 3 AET interrupt 10 None This system event is not connected and therefo...

Page 125: ...A3CC completion interrupt Mask0 72 EDMA3CC_INT1 EDMA3CC completion interrupt Mask1 73 EDMA3CC_INT2 EDMA3CC completion interrupt Mask2 74 EDMA3CC_INT3 EDMA3CC completion interrupt Mask3 75 EDMA3CC_INT4...

Page 126: ...ngle bit error detected 117 1 L2_ED2 L2 two bit error detected 118 1 PDC_INT Powerdown sleep interrupt Reserved These system events are not connected and therefore 119 Reserved not used 120 1 L1P_CMPA...

Page 127: ...r External Interrupts 1 see Figure 7 6 720 850 A 1000 1000 NO UNIT 1200 MIN MAX 1 tw NMIL Width of the NMI interrupt pulse low 6P ns 2 tw NMIH Width of the NMI interrupt pulse high 6P ns 1 P 1 CPU clo...

Page 128: ...the power supplies have reached their normal operating conditions Note that a device power up cycle is not required to initiate a Power on Reset The following sequence must be followed during a Power...

Page 129: ...m Reset 1 Hold the RESET pin low for a minimum of 24 CLKIN1 cycles Within the minimum 24 CLKIN1 cycles Within the low period of the RESET pin the following happens The Z group pins low group pins and...

Page 130: ...t signals flow to the entire chip resetting all the modules on chip except the test and emulation logic The PLL controllers are not reset Internal system clocks are unaffected If PLL1 PLL2 were locked...

Page 131: ...If any of the above reset sources occur simultaneously the PLLCTRL only processes the highest priority reset request The rest request priorities are as follows high to low Power on Reset Maximum Rese...

Page 132: ...ed SRST MRST WRST POR R 0 R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Figure 7 7 Reset Type Status Register RSTYPE Hex Address 029A 00E4 Table 7 13 Reset Type Status Register...

Page 133: ...ldown Resistors Table 7 15 Switching Characteristics Over Recommended Operating Conditions During Reset 1 see Figure 7 9 720 850 A 1000 1000 NO PARAMETER UNIT 1200 MIN MAX 9 td PORH RSTATH Delay time...

Page 134: ...FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 A SYSREFCLK of the PLL2 controller runs at CLKIN2 10 B SYSCLK1 of PLL2 controller runs at SYSREFCLK 2 default C Power...

Page 135: ...p For more details on the use of the RESET pin see Section 7 6 Reset Controller B A reset signal is generated internally during a Warm Reset This internal reset signal has the same effect as the RESET...

Page 136: ...anufacturer Murata part number NFM18CC222R1C3 or NFM18CC223R1C3 All PLL external components C1 C2 and the EMI Filter must be placed as close to the C64x DSP device as possible For the best performance...

Page 137: ...D3 are always enabled B CLKIN1 is a 3 3 V signal Figure 7 10 PLL1 and PLL1 Controller As shown in Figure 7 10 the PLL1 controller generates several internal clocks including the system reference cloc...

Page 138: ...ation has completed Note that there is a minimum and maximum operating frequency for PLLREF PLLOUT SYSCLK4 and SYSCLK5 The PLL1 Controller must not be configured to exceed any of these constraints cer...

Page 139: ...RESS RANGE ACRONYM REGISTER NAME 029A 0000 029A 00E3 Reserved 029A 00E4 RSTYPE Reset Type Status Register Reset Controller 029A 00E8 029A 00FF Reserved 029A 0100 PLLCTL PLL Control Register 029A 0104...

Page 140: ...R W 0 R W 1 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Figure 7 11 PLL1 Control Register PLLCTL Hex Address 029A 0100 Table 7 19 PLL1 Control Register PLLCTL Field Descript...

Page 141: ...ad only n value after reset Figure 7 12 PLL Multiplier Control Register PLLM Hex Address 029A 0110 Table 7 20 PLL Multiplier Control Register PLLM Field Descriptions Bit Field Value Description 31 5 R...

Page 142: ...PLL Pre Divider Control Register PREDIV Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no eff...

Page 143: ...LL Controller Divider 4 Register PLLDIV4 Hex Address 029A 0160 Table 7 22 PLL Controller Divider 4 Register PLLDIV4 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserve...

Page 144: ...V5 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 Dn4EN Divider 4 enable bit 0 Di...

Page 145: ...Bit Field Value Description 31 2 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 1 Reserved Reserved The reserved bit location is always...

Page 146: ...alue after reset Figure 7 17 PLL Controller Status Register PLLSTAT Hex Address 029A 013C Table 7 25 PLL Controller Status Register PLLSTAT Field Descriptions Bit Field Value Description 31 1 Reserved...

Page 147: ...it Field Value Description 31 5 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 4 3 ALNn SYSCLKn alignment Do not change the default value...

Page 148: ...Status Register DCHANGE Hex Address 029A 0144 Table 7 27 PLLDIV Divider Ratio Change Status Register DCHANGE Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved The reserved bit lo...

Page 149: ...R 1 R 1 R 1 LEGEND R Read only n value after reset Figure 7 20 SYSCLK Status Register SYSTAT Hex Address 029A 0150 Table 7 28 SYSCLK Status Register SYSTAT Field Descriptions Bit Field Value Descript...

Page 150: ...ee Section 7 7 1 2 PLL1 Controller Operating Modes 3 C CLKIN1 cycle time in ns For example when CLKIN1 frequency is 50 MHz use C 20 ns 4 The PLL1 multiplier factors x1 BYPASS x 15 x20 x25 x30 x32 furt...

Page 151: ...xternal components C161 C162 and the EMI Filter should be placed as close to the C64x DSP device as possible For the best performance TI requires that all the PLL external components be on a single si...

Page 152: ...YSCLK3 of the PLL2 controller Note that there is a minimum and maximum operating frequency for PLLREF PLLOUT and SYSCLK1 The clock generator must not be configured to exceed any of these constraints F...

Page 153: ...0148 Reserved 029C 014C Reserved 029C 0150 SYSTAT SYSCLK Status Register 029C 0154 029C 0190 Reserved 029C 0194 029C 01FF Reserved 029C 0200 029C FFFF Reserved This section provides a description of t...

Page 154: ...029C 0118 Table 7 33 PLL Controller Divider 1 Register PLLDIV1 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written t...

Page 155: ...Bit Field Value Description 31 2 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 1 Reserved Reserved The reserved bit location is always...

Page 156: ...peration is in progress SYSCLK divide ratios are being changed The PLL controller clock align control register ALNCTL is shown in Figure 7 27 and described in Table 7 36 31 16 Reserved R 0 15 1 0 Rese...

Page 157: ...LEGEND R W Read Write R Read only n value after reset Figure 7 28 PLLDIV Divider Ratio Change Status Register DCHANGE Hex Address 029C 0144 Table 7 37 PLLDIV Divider Ratio Change Status Register DCHA...

Page 158: ...0 15 1 0 Reserved SYS1ON R 0 R 1 LEGEND R W Read Write R Read only n value after reset Figure 7 29 SYSCLK Status Register Hex Address 029C 0150 Table 7 38 SYSCLK Status Register Field Descriptions Bit...

Page 159: ...uration CLKIN2 high 0 4C ns 3 tw CLKIN2L Pulse duration CLKIN2 low 0 4C ns 4 tt CLKIN2 Transition time CLKIN2 1 2 ns 5 tJ CLKIN2 Period jitter peak to peak CLKIN2 100 ps 1 The reference points for the...

Page 160: ...n to ensure all DDR2 interface timings in this solution are met The complete DDR2 system solution is documented in the Implementing DDR2 PCB Layout on the TMS320C6455 application report literature num...

Page 161: ...served 7800 0020 BPRIO DDR2 Memory Controller Burst Priority Register 7800 0024 7800 004C Reserved 7800 0050 7800 0078 Reserved 7800 007C 7800 00BC Reserved 7800 00C0 7800 00E0 Reserved 7800 00E4 DMCC...

Page 162: ...e data to the EMIFA For example if master A passes a software message via a buffer in external memory and does not wait for indication that the write completes when master B attempts to read the softw...

Page 163: ...2CFG EMIFA CE2 Configuration Register 7000 0084 CE3CFG EMIFA CE3 Configuration Register 7000 0088 CE4CFG EMIFA CE4 Configuration Register 7000 008C CE5CFG EMIFA CE5 Configuration Register 7000 0090 70...

Page 164: ...IN 2 ns 5 tJ EKI Period Jitter AECLKIN 0 02E 4 ns 1 The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN 2 E the EMIF input clock AECLKIN or SYSCLK4 period in ns...

Page 165: ...EMIFA Figure 7 32 AECLKOUT Timing for the EMIFA Module Table 7 44 Timing Requirements for Asynchronous Memory Cycles for EMIFA Module 1 2 3 see Figure 7 33 and Figure 7 34 720 850 A 1000 1000 NO UNIT...

Page 166: ...T 1200 MIN MAX 1 tosu SELV AOEL Output setup time select signals valid to AAOE low RS E 1 5 ns 2 toh AOEH SELIV Output hold time AAOE high to select signals invalid RS E 1 9 ns 10 td EKOH AOEV Delay t...

Page 167: ...gh the AP field of the EMIFA Async Wait Cycle Configuration register AWCC DEASSERTED AECLKOUT AARDY A ASSERTED DEASSERTED Strobe Hold 2 Extended Strobe Strobe Setup 2 A Polarity of the AARDY signal is...

Page 168: ...5 td EKOH EAIV Delay time AECLKOUT high to AEAx invalid 1 3 ns 8 td EKOH ADSV Delay time AECLKOUT high to ASADS ASRE valid 1 3 4 9 ns 9 td EKOH OEV Delay time AECLKOUT high to ASOE valid 1 3 4 9 ns 1...

Page 169: ...OE B AAWE ASWE B BE1 BE2 BE3 BE4 Q1 Q2 Q3 Q4 12 11 3 1 12 10 4 2 1 8 5 8 EA1 EA2 EA3 EA4 10 A The following parameters are programmable via the EMIFA Chip Select n Configuration Register CESECn Read l...

Page 170: ...or synchronous FIFO interface ACEx is active when ASOE is active CE_EXT 1 Function of ASADS ASRE R_ENABLE For standard SBSRAM or ZBT SRAM interface ASADS ASRE acts as ASADS with deselect cycles R_ENAB...

Page 171: ...MIN MAX 1 td HOLDL EMHZ Delay time HOLD low to EMIFA Bus high impedance 2E 3 ns 2 td EMHZ HOLDAL Delay time EMIF Bus high impedance to HOLDA low 0 2E ns 4 td HOLDH EMLZ Delay time HOLD high to EMIF B...

Page 172: ...tching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles for EMIFA Module see Figure 7 40 720 850 A 1000 1000 NO PARAMETER UNIT 1200 MIN MAX 1 td AEKOH ABUSRV Delay time AECL...

Page 173: ...g the I2C module ensure there are external pullup resistors on the SDA and SCL pins The I2C modules on the C6455 may be used by the DSP to control local peripherals ICs DACs ADCs etc or may be used to...

Page 174: ...Address Control Address Own I2CMDR I2CCNT Mode Data Count Vector Interrupt Interrupt Status I2CIVR I2CSTR Mask Status Interrupt I2CIMR Interrupt DMA I2C Module I2C Clock Shading denotes control statu...

Page 175: ...02B0 4014 ICCNT I2C data count register 02B0 4018 ICDRR I2C data receive register 02B0 401C ICSAR I2C slave address register 02B0 4020 ICDXR I2C data transmit register 02B0 4024 ICMDR I2C mode registe...

Page 176: ...re SDA high for 13 tsu SCLH SDAH 4 0 6 s STOP condition 14 tw SP Pulse duration spike must be suppressed 0 50 ns 15 Cb 5 Capacitive load for each bus line 400 400 pF 1 The I2C pins SDA and SCL do not...

Page 177: ...ulse duration SCL low 4 7 1 3 s 20 tw SCLH Pulse duration SCL high 4 0 6 s 21 td SDAV SDLH Delay time SDA valid to SCL high 250 100 ns Valid time SDA valid after SCL low For I2 C 22 tv SDLL SDAV 0 0 0...

Page 178: ...epeated Start Stop SDA SCL 16 26 24 SM320C6455 EP FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 Figure 7 43 I2C Transmit Timings C64x Peripheral Information and Ele...

Page 179: ...t does not have any access to this register 0288 0008 0288 0024 Reserved 0288 0028 Reserved 0288 002C Reserved The Host and the CPU have 0288 0030 HPIC HPI control register read write access to the HP...

Page 180: ...up time select signals 3 valid before HSTROBE low 5 ns 16 th HSTBL SELV Hold time select signals 3 valid after HSTROBE low 5 ns 17 tsu HDV HSTBH Setup time host data valid before HSTROBE high 5 ns 18...

Page 181: ...HSTBH HRDYH Delay time HSTROBE high to HRDY high 12 ns Case 1 HPID read with no 10 M 20 auto increment 3 Delay time HSTROBE low to 6 td HSTBL HRDYL ns HRDY low Case 2 HPID read with auto increment 10...

Page 182: ...XOR HDS2 OR HCS B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on HRDY may or may not...

Page 183: ...S HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transition...

Page 184: ...HDS1 XOR HDS2 OR HCS B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on HRDY may or may...

Page 185: ...n HCS HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transi...

Page 186: ...ite or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on HRDY may or may not occur For more detailed information on the HP...

Page 187: ...type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on HRDY may or may not occur For more detailed information...

Page 188: ...rite or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on HRDY may or may not occur For more detailed information on the H...

Page 189: ...type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on HRDY may or may not occur For more detailed informatio...

Page 190: ...and transmit Direct interface to industry standard codecs analog interface chips AICs and other serially connected analog to digital A D and digital to analog D A devices External shift clock or an in...

Page 191: ...only read 028C 0000 DRR0 McBSP0 Data Receive Register via Configuration Bus this register they cannot write to it 3000 0000 DRR0 McBSP0 Data Receive Register via EDMA3 Bus 028C 0004 DXR0 McBSP0 Data...

Page 192: ...generator register 0290 0018 MCR1 McBSP1 multichannel control register McBSP1 Enhanced Receive Channel Enable 0290 001C RCERE01 Register 0 Partition A B McBSP1 Enhanced Transmit Channel Enable 0290 00...

Page 193: ...es must be met even when CLKR X is generated by an internal clock source The minimum CLKR X cycle times are based on internal logic speed the maximum usable speed may be lower due to EDMA limitations...

Page 194: ...D1 9 5 6 D2 9 14 td FXH DXV ns ONLY applies when in data FSX ext 1 9 D1 9 9 D2 9 delay 0 XDATDLY 00b mode 7 C H or L S sample rate generator input clock 6P if CLKSM 1 P 1 CPU clock frequency S sample...

Page 195: ...UARY 2008 A Parameter No 13 applies to the first data bit only when XDATDLY 0 B The CLKS signal is shared by both McBSP0 and McBSP1 on this device Figure 7 52 McBSP Timing B Table 7 61 Timing Requirem...

Page 196: ...is CKXL DXHZ L 2 L 3 ns last data bit from CLKX low Disable time DX high impedance following 7 tdis FXH DXHZ 6P 3 18P 17 ns last data bit from FSX high 8 td FXL DXV Delay time FSX low to DX valid 12P...

Page 197: ...ble time DX high impedance following 6 tdis CKXL DXHZ 2 4 18P 3 30P 17 ns last data bit from CLKX low 7 td FXL DXV Delay time FSX low to DX valid H 2 H 4 12P 2 24P 17 ns 1 P 1 CPU clock frequency in n...

Page 198: ...is CKXH DXHZ H 2 H 3 ns last data bit from CLKX high Disable time DX high impedance following 7 tdis FXH DXHZ 6P 3 18P 17 ns last data bit from FSX high 8 td FXL DXV Delay time FSX low to DX valid 12P...

Page 199: ...ble time DX high impedance following 6 tdis CKXH DXHZ 2 4 18P 3 30P 17 ns last data bit from CLKX high 7 td FXL DXV Delay time FSX low to DX valid L 2 L 4 12P 2 24P 17 ns 1 P 1 CPU clock frequency in...

Page 200: ...2 3 2000 E Deviation from this standard the EMAC module does not use the Transmit Coding Error signal MTXER Instead of driving the error pin when an underflow condition occurs on a transmitted frame t...

Page 201: ...and control pins Therefore the EMAC conforms to the RGMII ID operation of the RGMII specification However the EMAC does not delay the receive clock RXC this signal must be delayed with respect to the...

Page 202: ...UXCLAV GMTCLK GMTCLK H1 URCLK MRCLK MRCLK MRCLK N4 UXCLK MTCLK REFCLK MTCLK RMREFCLK MTCLK N3 UXADDR3 GMDIO MDIO MDIO MDIO M5 UXADDR4 GMDCLK MDCLK MDCLK MDCLK Using the RMII Mode of the EMAC The Ethe...

Page 203: ...on see Section 7 8 PLL2 and PLL2 Controller The EMAC uses SYSCLK1 of the PLL2 Controller to generate the necessary clocks for the GMII and RGMII modes When these modes are used the frequency of CLKIN2...

Page 204: ...1BC MACINTMASKCLEAR MAC Interrupt Mask Clear Register 02C8 00C0 02C8 00FC Reserved 02C8 0100 RXMBPENABLE Receive Multicast Broadcast Promiscuous Channel Enable Register 02C8 0104 RXUNICASTSET Receive...

Page 205: ...MACADDRHI matching 02C8 0508 MACINDEX MAC Index Register 02C8 050C 02C8 05FC Reserved 02C8 0600 TX0HDP Transmit Channel 0 DMA Head Descriptor Pointer Register 02C8 0604 TX1HDP Transmit Channel 1 DMA H...

Page 206: ...n Pointer Interrupt Acknowledge 02C8 067C RX7CP Register 02C8 0680 02C8 06FC Reserved Reserved was State RAM Test Access Registers 02C8 0700 02C8 077C Processor Read and Write Access to Head Descripto...

Page 207: ...smit Octet Frames Register 02C8 0268 FRAME64 Transmit and Receive 64 Octet Frames Register 02C8 026C FRAME65T127 Transmit and Receive 65 to 127 Octet Frames Register 02C8 0270 FRAME128T255 Transmit an...

Page 208: ...lse duration MRCLK high 2 8 14 140 ns 3 tw MRCLKL Pulse duration MRCLK low 2 8 14 140 ns 4 tt MRCLK Transition time MRCLK 1 3 3 ns Figure 7 59 MRCLK Timing EMAC Receive MII and GMII Operation Table 7...

Page 209: ...ransition time GMTCLK 1 ns Figure 7 61 GMTCLK Timing EMAC Transmit GMII Operation Table 7 78 Timing Requirements for EMAC MII and GMII Receive 10 100 1000 Mbit s 1 see Figure 7 62 720 850 A 1000 1000...

Page 210: ...25 ns 1 For MII Transmit selected signals include MTXD 3 0 and MTXEN For GMII Transmit selected signals include GMTXD 7 0 and MTXEN Figure 7 63 EMAC Transmit Interface Timing MII and GMII Operation T...

Page 211: ...NO PARAMETER UNIT 1200 MIN MAX 1 tw RMREFCLKH Pulse duration RMREFCLK high 7 13 ns 2 tw RMREFCLKL Pulse duration RMREFCLK low 7 13 ns 3 tt RMREFCLK Transition time RMREFCLK 2 ns Figure 7 65 RMREFCLK T...

Page 212: ...720 850 A 1000 1000 NO UNIT 1200 MIN MAX Setup time receive selected signals valid before MREFCLK at DSP 1 tsu MRXD MREFCLK 4 0 ns high low 2 th MREFCLK MRXD Hold time receive selected signals valid...

Page 213: ...RGREFCLK 8 0 8 8 0 8 ns 2 tw RGFCLKH Pulse duration RGREFCLK high 3 2 4 8 ns 3 tw RGFCLKL Pulse duration RGREFCLK low 3 2 4 8 ns 4 tt RGFCLK Transition time RGREFCLK 0 75 ns Figure 7 68 RGREFCLK Timi...

Page 214: ...7 4 on the falling edge of RXC Similarly RXCTL carries RXDV on rising edge of RXC and RXERR on falling edge B RXC must be externally delayed relative to the data and control pins Figure 7 69 EMAC Rece...

Page 215: ...re TXC at DSP high low 1 2 ns 6 th TXCH TXD Hold time transmit selected signals valid after TXC at DSP high low 1 2 1 For RGMII transmit selected signals include TXD 3 0 and TXCTL A Data and control i...

Page 216: ...are used in the MII GMII and RMII modes on the MDIO For more detailed information on the EMAC MDIO see the TMS320C645x DSP EMAC MDIO Module Reference Guide literature number SPRU975 Clocking Informati...

Page 217: ...se duration MDCLK low 180 ns 3 tt MDCLK Transition time MDCLK 5 ns 4 tsu MDIO MDCLKH Setup time MDIO data input valid before MDCLK high 10 ns 5 th MDCLKH MDIO Hold time MDIO data input valid after MDC...

Page 218: ...294 0004 EMUMGT_CLKSPD0 Register 0294 0008 Reserved 0294 000C Reserved 0294 0010 CNTLO0 Timer 0 Counter Register Low 0294 0014 CNTHI0 Timer 0 Counter Register High 0294 0018 PRDLO0 Timer 0 Period Regi...

Page 219: ...w 12P ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns Table 7 95 Switching Characteristics Over Recommended Operating Conditions for Timer Outputs 1 see Figure...

Page 220: ...O lengths For more detailed information on the VCP2 see the TMS320C645x DSP Viterbi Decoder Coprocessor 2 VCP2 Reference Guide literature number SPRU972 Table 7 96 VCP2 Registers EDMA BUS CONFIGURATIO...

Page 221: ...hird Generation Partnership Projects 3GPP and 3GPP2 with fully programmable frame length and turbo interleaver Decoding parameters such as the number of iterations and stopping criteria are also progr...

Page 222: ...on Register 12 5000 0034 TCPIC13 TCP2 Input Configuration Register 13 5000 0038 TCPIC14 TCP2 Input Configuration Register 14 5000 003C TCPIC15 TCP2 Input Configuration Register 15 5000 0040 TCPOUT0 TC...

Page 223: ...read from an I2C EEPROM Table 7 98 shows the registers which can be initialized through the PCI auto initialization Also shown is the default value of these registers when PCI auto initialization is n...

Page 224: ...Revision ID 0x0C PCICLINE BIST Header Type Latency Timer Cacheline Size 0x10 PCIBAR0 Base Address 0 0x14 PCIBAR1 Base Address 1 0x18 PCIBAR2 Base Address 2 0x1C PCIBAR3 Base Address 3 0x20 PCIBAR4 Bas...

Page 225: ...K PCI Base Address Mask Register 5 02C0 0128 02C0 012B Reserved 02C0 012C PCISUBIDMIR PCI Subsystem Vendor ID Subsystem ID Mirror Register 02C0 0130 Reserved 02C0 0134 PCICPBPTRMIR PCI Capabilities Po...

Page 226: ...Register 02C0 0340 PCIADDSUB11 PCI Address Substitute 11 Register 02C0 0344 PCIADDSUB12 PCI Address Substitute 12 Register 02C0 0348 PCIADDSUB13 PCI Address Substitute 13 Register 02C0 034C PCIADDSUB1...

Page 227: ...er 3 Program Register 02C0 03D8 PCIBAR4PRG PCI Base Address Register 4 Program Register 02C0 03DC PCIBAR5PRG PCI Base Address Register 5 Program Register 02C0 03E0 PCIBAR0TRLPRG PCI Base Address Trans...

Page 228: ...7F FFFF PCI Master Window 20 4A80 0000 4AFF FFFF PCI Master Window 21 4B00 0000 4B7F FFFF PCI Master Window 22 4B80 0000 4BFF FFFF PCI Master Window 23 4C00 0000 4C7F FFFF PCI Master Window 24 4C80 00...

Page 229: ...ations as required by the PCI Local Bus Specification version 2 3 The AC timing specifications are not reproduced here For more information on the AC timing specifications see section 4 2 3 Timing Spe...

Page 230: ...e servicing For more detailed information on the UTOPIA peripheral see the TMS320C645x DSP Universal Test and Operations PHY Interface for ATM 2 UTOPIA2 User s Guide literature number SPRUE48 Table 7...

Page 231: ...nsition time UXCLK 2 ns 1 The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN Figure 7 74 UXCLK Timing Table 7 107 Timing Requirements for URCLK 1 see Figure 7 7...

Page 232: ...me UXENB low before UXCLK high 4 ns 9 th UXCH UXENBL Hold time UXENB low after UXCLK high 1 ns Table 7 109 Switching Characteristics Over Recommended Operating Conditions for UTOPIA Slave Transmit Cyc...

Page 233: ...e URADDR valid after URCLK high 1 ns 9 tsu URENBL URCH Setup time URENB low before URCLK high 4 ns 10 th URCH URENBL Hold time URENB low after URCLK high 1 ns 11 tsu URSH URCH Setup time URSOC high be...

Page 234: ...in terms of data manual specifications and I O buffer information specification IBIS models For the C6455 SRIO Port Texas Instruments TI provides a printed circuit board PCB solution showing two DSPs...

Page 235: ...0A8 RIO_PF_16B_CNTL3 Packet Forwarding Register 3 for 16 bit Device IDs 02D0 00AC RIO_PF_8B_CNTL3 Packet Forwarding Register 3 for 8 bit Device IDs 02D0 00B0 02D0 00FC Reserved 02D0 0100 RIO_SERDES_CF...

Page 236: ...egister 02D0 027C Reserved 02D0 0280 RIO_DOORBELL0_ICRR DOORBELL0 Interrupt Condition Routing Register 02D0 0284 RIO_DOORBELL0_ICRR2 DOORBELL 0 Interrupt Condition Routing Register 2 02D0 0288 02D0 02...

Page 237: ...INTDST Interrupt Rate Control Register 4 02D0 0334 RIO_INTDST5_RATE_CNTL INTDST Interrupt Rate Control Register 5 02D0 0338 RIO_INTDST6_RATE_CNTL INTDST Interrupt Rate Control Register 6 02D0 033C RIO...

Page 238: ...ransmit DMA Head Descriptor Pointer Register 13 02D0 0538 RIO_QUEUE14_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 14 02D0 053C RIO_QUEUE15_TXDMA_HDP Queue Transmit DMA Head Descripto...

Page 239: ...P Queue Receive DMA Completion Pointer Register 7 02D0 06A0 RIO_QUEUE8_RXDMA_CP Queue Receive DMA Completion Pointer Register 8 02D0 06A4 RIO_QUEUE9_RXDMA_CP Queue Receive DMA Completion Pointer Regis...

Page 240: ...ping Register L10 02D0 0854 RIO_RXU_MAP_H10 Mailbox to Queue Mapping Register H10 02D0 0858 RIO_RXU_MAP_L11 Mailbox to Queue Mapping Register L11 02D0 085C RIO_RXU_MAP_H11 Mailbox to Queue Mapping Reg...

Page 241: ...Table Entry Register 0 02D0 0904 RIO_FLOW_CNTL1 Flow Control Table Entry Register 1 02D0 0908 RIO_FLOW_CNTL2 Flow Control Table Entry Register 2 02D0 090C RIO_FLOW_CNTL3 Flow Control Table Entry Regi...

Page 242: ...RERIO_SP Port 1 Link Maintenance Response CSR 02D0 1168 RIO_SP1_ACKID_STAT Port 1 Local Acknowledge ID Status CSR 02D0 116C 02D0 1174 Reserved 02D0 1178 RIO_SP1_ERR_STAT Port 1 Error and Status CSR 02...

Page 243: ...re CSR 3 02D0 2098 RIO_SP1_ERR_CAPT_DBG4 Port 1 Packet Control Symbol Error Capture CSR 4 02D0 209C 02D0 20A4 Reserved 02D0 20A8 RIO_SP1_ERR_RATE Port 1 Error Rate CSR 02D0 20AC RIO_SP1_ERR_THRESH Por...

Page 244: ...er Register 02D1 410C RIO_SP1_MULT_EVNT_CS Port 1 Multicast Event Control Symbol Request Register 02D1 4110 Reserved 02D1 4114 RIO_SP1_CS_TX Port 1 Control Symbol Transmit Register 02D1 4118 02D1 41FC...

Page 245: ...ROCESSOR SPRS462B SEPTEMBER 2007 REVISED JANUARY 2008 TI only supports designs that follow the board design guidelines outlined in the SPRAAA8 application report Submit Documentation Feedback C64x Per...

Page 246: ...ANGE ACRONYM REGISTER NAME 02B0 0008 BINTEN GPIO interrupt per bank enable register 02B0 000C Reserved 02B0 0010 DIR GPIO Direction Register 02B0 0014 OUT_DATA GPIO Output Data register 02B0 0018 SET_...

Page 247: ...tware polling of the GPIO register the GPIx duration must be extended to at least 24P to allow the DSP enough time to access the GPIO register through the CFGBUS Table 7 115 Switching Characteristics...

Page 248: ...tate Sequencing allows combinations of hardware program breakpoints and data watchpoints to precisely generate events for complex sequences For more information on AET see the following documents Usin...

Page 249: ...controllers may not drive TRST high but expect the use of an external pullup resistor on TRST When using this type of JTAG controller assert TRST to initialize the DSP after powerup and externally dri...

Page 250: ...0 83 ns C6455 1200 1 2 GHz CPU Cycle Time Added 1200 device to 1 25 V Core Voltage Section 2 8 2 Device Support Added Device Speed Range 2 1 2 GHz to Figure 2 13 C64x DSP Device Nomenclature including...

Page 251: ...m s 1 1 R JC Junction to case 1 45 N A 2 R JB Junction to board 8 34 N A 3 16 1 0 00 4 13 0 1 0 R JA Junction to free air 5 11 9 2 0 6 10 7 3 0 0 37 0 00 0 89 1 0 7 PsiJT Junction to package top 1 01...

Page 252: ...gh temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used be...

Page 253: ......

Page 254: ...ce TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonabl...

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