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Reset

2-4

Table 2–1. Sampling Frequencies for Various MCLK and Register 4 Values

Reg 4, Bit 7

Reg 4, Bits 6–4

8.192 MHz

10.000 MHz

10.240 MHz

11.2896 MHz

0 (default)

8 kHz

9.765 kHz

10 kHz

11.025 kHz

1

(64 kHz)

(78.125 kHz)

(80 kHz)

(88.2 kHz)

2

(32 kHz)

(39.063kHz)

(40 kHz)

(44.1 kHz)

bit 7 = 0

3

21.333 kHz

(26.042 kHz)

(26.666 kHz)

(29.4 kHz)

PLL on

4

16 kHz

19.531 kHz

20 kHz

22.05 kHz

5

12.8 kHz

15.625 kHz

16 kHz

17.64 kHz

6

10.666 kHz

13.021 kHz

13.333 kHz

14.7 kHz

7

9.1432 kHz

11.161 kHz

11.429 kHz

12.601 kHz

0

2 kHz

2.441 kHz

2.500 kHz

2.756 kHz

1

16 kHz

19.531 kHz

20 kHz

22.05 kHz

2

8 kHz

9.766 kHz

10 kHz

11.025 kHz

bit 7 = 1

3

5.333 kHz

6.510 kHz

6.666 kHz

7.35 kHz

PLL off

4

4 kHz

4.883 kHz

5 kHz

5.513 kHz

5

3.2 kHz

3.906 kHz

4 kHz

4.41 kHz

6

2.666 kHz

3.255 kHz

3.333 kHz

3.675 kHz

7

0.798 kHz

2.79 kHz

2.857 kHz

3.15 kHz

2.4

Reset

In all operating modes the AD50-EVM is reset when the power is switched on.
In DSK+ mode it is also reset when the DSK+ itself is reset. The programmable
logic on the AD50-EVM is configured so that in the reset state all the AD50s
are powered down and in slave mode and that the AC01 on the DSK+ is pow-
ered up as normal. This means that even with one or two AD50-EVMs attached
to a DSK+ system, all the DSK+ demonstration software works normally with
the AC01 AIC.

To use one or more AD50s it is necessary to program bits 0-3 of I/O address
0. Bit 0 controls the reset state of the AD50s. Bit 0 = 0 resets all AD50s and
bit 0 = 1 allows them to run. Bits 1, 2, and 3 are encoded to control the number
of AD50s that are powered up (see Table B–1 for details). Note that no provi-
sion has been made to operate the AD50s and the AC01 together. This is be-
cause their control registers are incompatible and it would be difficult to pre-
vent bus conflicts on the serial interface.

The reset pins are connected to both the SERIAL and CONTROL cable head-
ers for use in standalone mode (see Table A–2 for pinouts).

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Summary of Contents for SLAU039

Page 1: ...Evaluation Board for the TLC320AD50C DSP Analog Interface Circuit 2000 Mixed Signal Products User s Guide SLAU039 ...

Page 2: ...CONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to ...

Page 3: ... B Programmable Logic Appendix C Converting DSK Software for the AD50 EVM Notational Conventions This document uses the following conventions Program listings program examples and interactive displays are shown in a special typeface similar to a typewriter s Examples use a bold version of the special typeface for emphasis interactive displays use a bold version of the special typeface to distingui...

Page 4: ...u don t enter the brackets themselves Here s an example of an instruction that has an optional parameter LALK 16 bit constant shift The LALK instruction has two parameters The first parameter 16 bit con stant is required The second parameter shift is optional As this syntax shows if you use the optional second parameter you must precede it with a comma Square brackets are also used as part of the ...

Page 5: ...plifier Selection Guide Literature number SLOBE02 Single Supply Operational Amplifier Selection Guide Literature number SLOBE03 Mixed Signal Analog CD ROM Literature number SLYC005 TMS320C54x CPU and Peripherals Literature number SPRU131 TMS320C54x Algebraic Instruction Set Literature number SPRU179 TMS320C54x DSKplus User s Guide Literature number SPRU191 Much useful software is available from th...

Page 6: ...vi ...

Page 7: ...p Design 2 6 2 6 2 Input Stage Design 2 6 2 6 3 Op Amp Selection 2 7 2 6 4 Antialiasing Filter 2 8 2 7 Analog Output 2 9 3 Setting Up the AD50 EVM 3 1 3 1 Setting Up the AD50 EVM With the DSK 3 2 3 2 Setting Up the AD50 EVM in Stand Alone Mode 3 2 3 3 Configuring the Serial Interface 3 2 3 4 Programming the AD50 Registers 3 3 3 5 Sine Wave Generator and Loopback Program 3 4 4 Results Obtained With...

Page 8: ...Running Title Attribute Reference viii B Programmable Logic B 1 B 1 DSK Mode B 2 B 2 Stand Alone Mode B 2 B 3 Logic Compiler Listing B 3 C Converting DSK Software for the AD50 EVM C 1 ...

Page 9: ...sing Filter Options 2 8 2 5 AD50 EVM Differential to Single Ended Output Converter 2 9 4 1 AD50 EVM ADC Distortion Measurement at 8 ksps 4 2 4 2 AD50 EVM ADC Distortion Measurement at 20 ksps 4 3 4 3 AD50 EVM DAC Distortion Measurement at 8 ksps 4 4 4 4 AD50 EVM DAC Distortion Measurement at 20 ksps 4 5 A 1 Diagram of the AD50 EVM A 2 ...

Page 10: ...bute Reference x Tables 2 1 Sampling Frequencies for Various MCLK and Register 4 Values 2 4 A 1 Jumper Positions A 2 A 2 Control and Serial Connections A 3 A 3 Analog Input Output Connectors A 3 B 1 AD50 EVM Registers B 2 ...

Page 11: ...ludes an interpolation filter before the DAC and a decimation filter after the ADC Other overhead functions provide on chip timing and control The sigma delta architecture pro duces high resolution analog to digital and digital to analog conversion at low system speeds and low cost The options and the circuit configurations of this device can be programmed through the serial interface The options ...

Page 12: ...system using a single serial interface The AD50 EVM can be interfaced directly to the DSK DSP starter kit or other sys tems which have a compatible synchronous serial interface The objective was to design a development board the AD50 EVM which would allow prospective users of the AD50 to determine its capabilities with a minimum effort The board can be directly connected to the low cost TMS320C54x...

Page 13: ...onversion The input signal is first buffered and optionally amplified by the preamp stage before being level shifted and converted to a differential pair of signals The external antialiasing filter is a simple continuous time filter to remove RF noise The output from the codec is converted to a single ended signal and is filtered to remove high frequency noise A negative power supply is generated ...

Page 14: ...age frequencies that would otherwise be present at the output of a conventional DAC This avoids the need for a high or der analog low pass reconstruction filter Separate sin x x compensation is not needed as this is inherent in the DAC architecture Sigma delta converters have several advantages and a few disadvantages relative to other types of ADC which are summarized below 1 3 1 Advantages Sigma...

Page 15: ...cause each channel would be corrupted by the earlier samples from other channels still propagating through the digital filter Although the AD50 has an input multiplexer this is only for selecting one or another input not for interleaving two input channels onto one data stream Audio band converters are optimized for ac signals and a small dc offset may be present Spurious low level tones can somet...

Page 16: ...1 6 ...

Page 17: ...on This chapter discusses the printed circuit board design considerations for the AD50 EVM Topic Page 2 1 PCB Construction 2 2 2 2 Power Supply 2 3 2 3 System Clock 2 3 2 4 Reset 2 4 2 5 Serial Port Interfacing 2 5 2 6 Analog Input 2 6 2 7 Analog Output 2 10 Chapter 2 ...

Page 18: ...arate connector has been provided for interfacing to systems other than the DSK This brings out the SCLK FS DIN DOUT and RESET signals Each signal is interleaved with a ground conductor in the ribbon cable allowing a longer cable length without crosstalk Nevertheless this cable should be as short as reasonably possible since ringing in the unterminated cable may be come excessive for lengths great...

Page 19: ...uencies that can be selected for a number of master clock frequencies Frequencies shown in brackets are above the maximum sampling frequency specified for the AD50 In standalone mode the AD50 EVM can be clocked at frequencies up to 22 579 MHz However when used in conjunction with the DSK the upper frequency is limited by the maximum clock rate of the TMS320C542 DSP device The 10 24 MHz oscillator ...

Page 20: ...50 EVM is reset when the power is switched on In DSK mode it is also reset when the DSK itself is reset The programmable logic on the AD50 EVM is configured so that in the reset state all the AD50s are powered down and in slave mode and that the AC01 on the DSK is pow ered up as normal This means that even with one or two AD50 EVMs attached to a DSK system all the DSK demonstration software works ...

Page 21: ...logic device as shown in Figure 2 1 The logic equations are listed in Appendix B The serial clock serial data in and serial data out signals are connected to all devices Only one device at a time drives these lines When two AD50 EVMs are used in standalone mode together with a separate DSP system the ribbon cable must be attached to the primary board so that the master device frame sync signal is ...

Page 22: ...N removed the preamp has uni ty gain from dc to 20 kHz With this link inserted the preamp gain is increased by 20 dB The signal can be ac coupled by removing the link labeled DC The use of two tantalum capacitors back to back allows 10 V dc voltage bias at the input without damaging the capacitors Figure 2 2 AD50 EVM Input Preamp _ 1 2 TLC2272 5 V 5 V 100 nF 100 nF 22 kΩ 1 nF 2 2 kΩ Gain 4 7 µF Ta...

Page 23: ...d that this device is likely to be used in predominantly digital de signs powered from a single 5 V supply where the need for a negative supply could be perceived as a problem However since the current drawn from this negative supply will be small it is possible to use an inverter chip to provide a local negative rail for the op amps The 7660 device requires no external in ductors and just 2 exter...

Page 24: ...on increases when driving loads of about 2 kΩ or less 2 6 4 Antialiasing Filter Sigma delta converters have the advantage of providing anti aliasing filtering as an integral part of their operation However this filtering has holes in it at multiples of the oversampling frequency The AD50 is a 64 times oversampling converter so for a sampling rate of 20 kHz the first hole will be centered at 1 28 M...

Page 25: ...bility of noise pickup between the filter and the ADC The use of 0603 footprint surface mount components makes this possible 2 7 Analog Output The AD50 uses a pair of differential voltage outputs The output stage needs to convert the differential signals to a single ended output and to attenuate noise outside the pass band This filter is not a conventional reconstruction fil ter since the AD50 has...

Page 26: ...2 10 ...

Page 27: ...assembler programs from a DOS or Windows environment Many example programs are supplied with the DSK which can readily be adapted to interface to the AD50 EVM See Appendix C for detailed information on adapting example programs The second configuration is standalone mode where a ribbon cable up to 1 m long connects the AD50 EVM to a separate DSP system In standalone mode some options such as the n...

Page 28: ...th the DSK Appendix C shows how OSCOPE was modified to work with the AD50 EVM 3 2 Setting Up the AD50 EVM in Stand Alone Mode In stand alone mode the AD50 EVM needs to be connected to a system with a suitable DSP serial interface This should include a means of controlling the RESET signal The connector marked SERIAL has all the necessary signals with interleaved grounds The POWERDOWN and other con...

Page 29: ...t DAC mode Once 16 bit mode has been selected it is not possible to request further secondary communications by setting bit 0 of a serial port data word However the AD50 EVM provides a means for driving the FC pin of the AD50 chip by writing to bit 0 of I O address 1 The value written is applied to the FC pin and a 1 initiates a hardware secondary communication request FC is sampled by the AD50 on...

Page 30: ...SKPLASM AD50SIN This generates a binary object file called AD50SIN OBJ which is loaded into the DSK as follows LOADAPP A AD50SIN OBJ title Sine wave generator for AD50 EVM and C54x DSK width 80 length 55 Adapted from DSK example programs by John Walliker and Julian Daley June 1997 mmregs setsect text 0x1800 0 these assembler directives specify setsect data 0x0200 1 the absolute addresses of differ...

Page 31: ...nable 48 external interrupt int2 nop nop nop tint return_enable 4C internal timer interrupt nop nop nop brint return_enable 50 BSP receive interrupt nop nop nop bxint return_enable 54 BSP transmit interrupt nop nop nop trint dgoto receive 58 TDM receive interrupt nop nop txint return_enable 5C TDM transmit interrupt nop nop nop int3 return_enable 60 external interrupt int3 nop nop nop hpiint goto ...

Page 32: ... RXINT and HPIINT tspc 0008h stop TDM serial port tdxr 0h send 0 as first xmit word tspc 00c8h reset and start TDM serial port ar1 0011b bring ad50 out of reset with one channel powered up port 0 ar1 initialize ad50 registers a 0000010010010000b register 4 call ad50init change fsamp to 20kHz a 0000001011000000b register 4 call ad50init light led a 0000000100000001b select 16 bit dac mode call ad50...

Page 33: ... nop if ALT execute 1 check whether index points outside table A B AR1 A A sinetable20_3dB AR2 prog A get sinewave value from table in program memory B AR2 could use sine table in rom for this endif if mode16bit 0 B 1111111111111110b mask least significant bit if in 15 bit mode to endif prevent inadvertent secondary communication requests mmr TDXR B restore context if necessary return_enable retur...

Page 34: ...3 8 ...

Page 35: ... Obtained With AD50 EVM Results Obtained With AD50 EVM This chapter describes the results possible with the AD50 EVM Actual mea surements are presented Topic Page 4 1 ADC Results 4 2 4 2 DAC Results 4 4 Chapter 4 ...

Page 36: ...erages Figure 4 1 shows an FFT plot obtained from the ADC of the AD50 EVM The input signal was a 1 2 kHz sine wave at 3 dB relative to maximum input A dig ital oscillator using a 20 bit DAC was used to produce the test signal By adding up the energy in each frequency bin within a the signal b the harmonics and c the rest of the noise floor figures for SNR SNR and SINAD can be calcu lated The figur...

Page 37: ... 110 130 0 1 2 3 4 5 6 Full Scale dB 40 10 f Frequency kHz 0 7 8 9 10 20 30 50 70 90 100 120 Input Signal 1 1 kHz 3 dB FFT 20 ksa s 2048 Frequency Bins 16 Averages Figure 4 2 shows an FFT plot obtained from the ADC while sampling at 20 ksps The performance figures were 82 7 dB SNR 81 0 dB SDR and 78 7 dB SINAD ...

Page 38: ...M acquisition system running at 40 ksps coupled to a DSP development system in a PC The signal to noise plus distortion ratio SINAD measured in the pass band excluding dc was 80 5 dB The SNR was 83 6 dB and the SDR was 83 4 dB These measurements have not been adjusted for the noise and distortion of the acquisition system The rise in the noise floor above 4 kHz is due to the digital noise shaping ...

Page 39: ...e made at 20 ksps The results were 78 6 dB SNR 84 8 dB SDR and 77 6 dB SINAD Again this has not been compensated for the characteristics of the acquisition system The spike at 10 kHz is caused by breakthrough from the negative supply gen erator The larger peaks above 16 kHz are images that have not been com pletely removed by the reconstruction filters These are well outside the pass band of the D...

Page 40: ...4 6 ...

Page 41: ... along with guidelines for connecting it to the DSK The parts list schematics gerber plots and board outline drawings are included Topic Page A 1 Board Outline Drawing With Jumper Locations on the AD50 EVM A 2 A 2 Connecting the AD50 EVM to the DSK A 4 A 3 Parts List A 4 A 4 Circuit Diagrams A 7 A 5 PCB Diagrams A Appendix A ...

Page 42: ...er Positions OPEN CLOSED DEFAULT L_DC Left channel ac input coupling Left channel dc input coupling OPEN R_DC Right channel ac input coupling Right channel dc input coupling OPEN L_GAIN Left channel 0 dB input gain Left channel 20 dB input gain OPEN R_GAIN Right channel 0 dB input gain Right channel 20 dB input gain OPEN PRI SEC Primary board Secondary board OPEN The connectors marked SERIAL and C...

Page 43: ...ROUND 12 RIGHT FLAG 13 GROUND 14 LEFT FLAG 14 GROUND 16 LEFT ALTDATA There are 4 sets of connectors that provide direct access to the analog I O pins of the AD50 The pinouts for these are shown in Table A 3 Table A 3 Analog Input Output Connectors Label Aux ip Diff op Mon out Left L_AUXIN L_OP L_MON Right R_AUXIN R_OP R_MON Pin Aux ip Diff op Mon out 1 AUXP OUTP MONOUT 2 1 25 V GROUND GROUND 3 AUX...

Page 44: ...e boards To allow development work with the AD50 EVM it is suggested that the sockets be sol dered to the bottom of the AD50 EVM and the pins to the top of the DSK This puts the AD50 EVM on top of the DSK and provides good access to the sig nals on the AD50 EVM If two AD50 EVM boards are being used in conjunction with a DSK then a different socket with pass through pins should be used on the middl...

Page 45: ... R77 10k R24 10K R78 4 7 k 4K7 R25 10K R79 4 7 k 4K7 R26 10K R80 4 7 k 4K7 R27 10K R81 10k R28 10K R82 10k R29 10K R83 470 470R R30 4 7 k 4K7 R84 470 470R R31 4 7 k 4K7 R85 10k R32 4 7 k 4K7 R86 10k R33 4 7 k 4K7 R87 10k R36 0 Ω link R88 10k R51 10K R89 10k R52 10K R90 10k R53 10K R91 10k R54 10K R92 10k R55 12K R93 10k R56 18K R94 10k R57 12K R95 10k R96 10k C30 100 nF X7R 0805 R97 10k C31 100 nF...

Page 46: ...0 nF X7R 0805 C71 22 pF COG NPO 0603 C13 100 nF X7R 0805 C72 100 µF 10 V size D tantalum C14 100 nF X7R 0805 C73 100 µF 10 V size D tantalum C15 100 nF X7R 0805 C74 100 nF X7R 0805 C16 100 nF X7R 0805 C75 100 nF X7R 0805 C17 100 nF X7R 0805 C76 100 µF 10V size D tantalum C21 4 7 µF 10 V size A tantalum C81 100 nF X7R 0805 C22 4 7 µF 10 V size A tantalum C82 100 nF X7R 0805 C23 470 pF COG NPO 0603 ...

Page 47: ...Circuit Diagrams A 7 Installing the AD50 EVM A 4 Circuit Diagrams ...

Page 48: ...A 8 ...

Page 49: ...A 9 Installing the AD50 EVM ...

Page 50: ...A 10 ...

Page 51: ...PCB Diagrams A 11 Installing the AD50 EVM A 5 PCB Diagrams Top Side Silkscreen ...

Page 52: ...A 12 1 Top Side Tracks Top Side Tracks ...

Page 53: ...A 13 Installing the AD50 EVM Bottom Side Tracks ...

Page 54: ...A 14 Ground plane ...

Page 55: ...A 15 Installing the AD50 EVM Power plane ...

Page 56: ...A 16 ...

Page 57: ...wise a pull up resistor makes it de fault to stand alone mode One or two AD50 EVM boards can provide 1 2 3 or 4 simultaneously sampled channels When two boards are coupled together the primary sec ondary jumper controls the daisy chaining of serial frame sync pulses and con trols the way that data from the DSK is interpreted Designers familiar with the AC01 should note that the power down behavior...

Page 58: ...omes the secondary one and has channels 3 and 4 The 22V10 must have a propagation delay of 25 ns or less assuming that one or more I O wait states are programmed in the TMS320C542 Zero wait state operation would have negligible benefit and would need a much faster and more costly device The AD50s are reset either when the DSK is reset or when a 0 is programmed into bit 0 of address 0 Reset must be...

Page 59: ... secondary board PIN 14 GRND PIN 15 NC2 PIN 16 DSK_present pulled low when DSK is connected PIN 17 sec_sfs secondary serial frame sync PIN 18 dsk_sfs serial frame sync to DSK PIN 19 fc control signal for initiating secondary comms PIN 20 AC01_pwrdn power down AC01 on DSK PIN 21 L_ms left master slave select PIN 22 NC3 PIN 23 L_pwrdn left power down PIN 24 R_pwrdn right power down PIN 25 AD50_rst r...

Page 60: ...ary select0 d3 d2 d1 primary select0 d3 d2 d1 select0 d3 d2 d1 select0 L_pwrdn L_pwrdn clkf iostrb L_pwrdn rstf DSK_reset L_pwrdn trst DSK_present L_ms primary L_pwrdn DSK_present primary DSK_present R_pwrdn select0 d3 d2 d1 primary select0 d3 d2 d1 primary select0 d3 d2 d1 select0 R_pwrdn R_pwrdn clkf iostrb R_pwrdn rstf DSK_reset R_pwrdn trst DSK_present DSK_sfs L_sfs DSK_sfs trst primary AC01_p...

Page 61: ...m code for single channel opera tion as the AD50 uses the same serial port as the AC01 However the AC01 is a 14 bit device whereas the AD50 supports 15 or 16 bit operations For best performance therefore masking operations that strip the two least significant bits from data sent to or from the AC01 should be modified to remove only bit 0 or removed completely depending on whether 15 or 16 bit mode...

Page 62: ...r ar2 data 0bh store to rcv buffer imr 40h intm 0 ready to rcv int s wait nop goto wait Receive Interrupt Routine RINT b trcv load acc b with input b 0FFFEh b only strip out lsb for AD50 ar2 data 0bh store to rcv buffer tdxr b transmit the data TC ar2 01300h if TC goto restrt stop if rcv buffer is at 1300h return_enable restrt ar2 1200h set intm bit no int s hpic 0ah flag host task completed retur...

Page 63: ...AD50 EVM 0000 0000 0000 0001 initialize Register 1 0000 0000 0000 0010 initialize Register 2 0000 0000 0000 0100 initialize Register 3 0000 0000 0000 1000 initialize Register 4 Any combination of registers can be initialized by adding the binary number to the REGISTER constant For example to initialize Registers 4 and 5 REGISTER 18h Upon assembly only code for register 4 5 initialization is includ...

Page 64: ...serial port tdxr 0h send 0 as first xmit word tspc 00c8h reset and start TDM serial port xf 1 release ac01 from reset ar2 0011b bring ad50 out of reset with 1 channel selected port 0 ar2 Register init s eval REGISTER 1h SELECT if REG1 then include this source if SELECT 1h a REG1 load Acc A with REG1 value call REQ2 Call REQ2 subroutine endif eval REGISTER 2h SELECT if REG2 then include this source...

Page 65: ... return end File osc_vecs ASM Vector Table for the C54x DSKplus Oscilloscope width 80 length 55 title Vector Table mmregs reset dgoto start 00 RESET IMR 200h nmi return_enable 04 non maskable external interrupt nop nop nop trap2 return_enable 08 trap2 nop nop nop space 52 16 0C 3F vectors for software interrupts 18 30 int0 return_enable 40 external interrupt int0 nop nop nop int1 return_enable 44 ...

Page 66: ...rrupt nop nop nop trint goto RINT 58 TDM receive interrupt nop nop txint return_enable 5C TDM transmit interrupt nop nop nop int3 return_enable 60 external interrupt int3 nop nop nop hpiint return_enable 64 HPIint nop nop nop space 24 16 68 7F reserved area ...

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