Texas Instruments Sitara AM3352, Manual

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Peripheral Information and Timings
Copyright © 2011–2016, Texas Instruments Incorporated
7.12 Multichannel Serial Port Interface (McSPI)
For more information, see the Multichannel Serial Port Interface (McSPI) section of the AM335x Sitara
Processors Technical Reference Manual ( SPRUH73 ).
7.12.1 McSPI Electrical Data and Timing
The following timings are applicable to the different configurations of McSPI in master or slave mode for
any McSPI and any channel (n).
7.12.1.1 McSPI—Slave Mode
Table 7-80. McSPI Timing Conditions – Slave Mode
PARAMETER MIN MAX UNIT
Input Conditions
t
r
Input signal rise time 5 ns
t
f
Input signal fall time 5 ns
Output Condition
C
load
Output load capacitance 20 pF
Table 7-81. Timing Requirements for McSPI Input Timings—Slave Mode
(see Figure 7-88 )
NO.
OPP100 OPP50
UNIT
MIN MAX MIN MAX
1 t
c(SPICLK)
Cycle time, SPI_CLK 62.5 124.8 ns
2 t
w(SPICLKL)
Typical pulse duration, SPI_CLK low
0.5P –
3.12
(1)
0.5P +
3.12
(1)
0.5P –
3.12
(1)
0.5P +
3.12
(1)
ns
3 t
w(SPICLKH)
Typical pulse duration, SPI_CLK high
0.5P –
3.12
(1)
0.5P +
3.12
(1)
0.5P –
3.12
(1)
0.5P +
3.12
(1)
ns
4 t
su(SIMO-SPICLK)
Setup time, SPI_D[x] (SIMO) valid before SPI_CLK
active edge
(2)(3)
12.92 12.92 ns
5 t
h(SPICLK-SIMO)
Hold time, SPI_D[x] (SIMO) valid after SPI_CLK
active edge
(2)(3)
12.92 12.92 ns
8 t
su(CS-SPICLK)
Setup time, SPI_CS valid before SPI_CLK first
edge
(2)
12.92 12.92 ns
9 t
h(SPICLK-CS)
Hold time, SPI_CS valid after SPI_CLK last edge
(2)
12.92 12.92 ns
(1) P = SPI_CLK period.
(2) This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to drive output data and
capture input data.
(3) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
Table 7-82. Switching Characteristics for McSPI Output Timings—Slave Mode
(see Figure 7-89 )
NO. PARAMETER
OPP100 OPP50
UNIT
MIN MAX MIN MAX
6 t
d(SPICLK-SOMI)
Delay time, SPI_CLK active edge to
SPI_D[x] (SOMI) transition
(1)(2)
–4.00 17.12 –4.00 17.12 ns
7 t
d(CS-SOMI)
Delay time, SPI_CS active edge to
SPI_D[x] (SOMI) transition
(1)(2)
17.12 17.12 ns
(1) This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to drive output data and
capture input data.
(2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.