Texas Instruments Sitara AM3352, Manual

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Texas Instruments Sitara AM3352 Manual Download Page 141

GPMC_FCLK

gpmc_clk

gpmc_csn[x]

gpmc_a[10:1]

gpmc_be0n_cle

gpmc_be1n

gpmc_advn_ale

gpmc_oen

gpmc_ad[15:0]

gpmc_wait[x]

Add0

Add1

Add2

Add3

Add4

D0

D1

D2

D3

D3

FA1

FA0

FA18

FA13

FA12

FA0

FA9

FA10

FA10

FA21

FA20

FA20

FA20

141

AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351

SPRS717J – OCTOBER 2011 – REVISED APRIL 2016

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Product Folder Links:

AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

Peripheral Information and Timings

Copyright © 2011–2016, Texas Instruments Incorporated

A.

In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.

B.

FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in
number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input
page data will be internally sampled by active functional clock edge. FA21 calculation must be stored inside
AccessTime register bits field.

C.

FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in
number of GPMC functional clock cycles. After each access to input page data, next input page data will be internally
sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address
phases for successive input page data (excluding first input page data). FA20 value must be stored in
PageBurstAccessTime register bits field.

D.

GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

Figure 7-24. GPMC and NOR Flash—Asynchronous Read—Page Mode 4x16-bit

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Summary of Contents for Sitara AM3352

Page 1: ...le ELM Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm Supports 4 8 and 16 Bit per 512 Byte Block Error Location Based on BCH Algorithms Programmable Real Time Unit Subsystem and Industrial Communication Subsystem PRU ICSS Supports Protocols such as EtherCAT PROFIBUS PROFINET EtherNet IP and More Two Programmable Real T...

Page 2: ...rsion 2 Parts A and B Up to Two Multichannel Audio Serial Ports McASPs Transmit and Receive Clocks up to 50 MHz Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks Supports Time Division Multiplexing TDM Inter IC Sound I2S and Similar Formats Supports Digital Audio Interface Transmission SPDIF IEC60958 1 and AES 3 Formats FIFO Buffers for Transmit and Receive 256 Bytes Up ...

Page 3: ... Modules Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs Up to Three Enhanced High Resolution PWM Modules eHRPWMs Dedicated 16 Bit Time Base Counter With Time and Frequency Controls Configurable as Six Single Ended Six Dual Edge Symmetric or Three Dual Edge Asymmetric Outputs Up to Three 32 Bit Enhanced Quadrature Encoder Pulse eQEP Modules Device Identification Contains Electr...

Page 4: ...it MPU subsystem is based on the ARM Cortex A8 processor and the PowerVR SGX Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects The PRU ICSS is separate from the ARM core allowing independent operation and clocking for greater efficiency and flexibility The PRU ICSS enables additional peripheral interfaces and real time protocols such as EtherCAT...

Page 5: ...tal Oscillator x2 MMC SD and SDIO x3 GPIO EMAC 2 port 10M 100M 1G IEEE 1588v2 and switch MII RMII RGMII mDDR LPDDR DDR2 DDR3 DDR3L 16 bit 200 266 400 400 MHz NAND and NOR 16 bit ECC Memory interface Copyright 2016 Texas Instruments Incorporated 5 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 www ti com SPRS717J OCTOBER 2011 REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links A...

Page 6: ...log to Digital Subsystem Electrical Parameters 97 6 Power and Clocking 99 6 1 Power Supplies 99 6 2 Clock Specifications 107 7 Peripheral Information and Timings 116 7 1 Parameter Information 116 7 2 Recommended Clock and Control Signal Transition Behavior 116 7 3 OPP50 Support 116 7 4 Controller Area Network CAN 117 7 5 DMTimer 118 7 6 Ethernet Media Access Controller EMAC and Switch 119 7 7 Exte...

Page 7: ...2016 Texas Instruments Incorporated 2 Revision History NOTE Page numbers for previous revisions may differ from page numbers in the current version Changes from Revision I December 2015 to Revision J Page Added Secure boot to Security feature list 3 Added extended temperature range for the AM3351 device in Table 3 1 8 Added Section 3 1 Related Products 9 Reformatted and added content to Section 8 ...

Page 8: ...128KB 128KB 128KB Display options LCD LCD LCD LCD LCD LCD LCD General purpose memory 1 16 bit GPMC NAND flash NOR flash SRAM 1 16 bit GPMC NAND flash NOR flash SRAM 1 16 bit GPMC NAND flash NOR flash SRAM 1 16 bit GPMC NAND flash NOR flash SRAM 1 16 bit GPMC NAND flash NOR flash SRAM 1 16 bit GPMC NAND flash NOR flash SRAM 1 16 bit GPMC NAND flash NOR flash SRAM DRAM 3 1 16 bit LPDDR 400 DDR2 532 ...

Page 9: ...requencies 3 1 Related Products For information about other devices in this family of products see the following links Sitara Processors Scalable processors based on ARM Cortex A cores with flexible peripherals connectivity and unified software support perfect for sensors to servers TI s ARM Cortex A8 Advantage The ARM Cortex A8 core is highly optimized by ARM for performance and power efficiency ...

Page 10: ... and Functions Copyright 2011 2016 Texas Instruments Incorporated 4 Terminal Configuration and Functions 4 1 Pin Diagrams NOTE The terms ball pin and terminal are used interchangeably throughout the document An attempt is made to use ball only when referring to the physical package 4 1 1 ZCE Package Pin Maps Top View The pin maps that follow show the pin assignments on the ZCE package in three sec...

Page 11: ... 16 WARMRSTn SPI0_CS1 XXXX XXXX XXXX VDDS 15 EMU0 XDMA_EVENT_INTR1 XDMA_EVENT_INTR0 XXXX PWRONRSTn XXXX 14 TDO TCK TMS EMU1 XXXX VDDSHV6 13 TRSTn TDI CAP_VBB_MPU CAP_VDD_SRAM_MPU VDDSHV6 VSS 12 AIN7 AIN5 VDDS_SRAM_MPU_BB VDDS VDDSHV6 VSS 11 AIN1 AIN3 XXXX XXXX VDDSHV6 VDD_CORE 10 AIN6 CAP_VDD_SRAM_CORE VDDS_SRAM_CORE_BG VSS VSS XXXX 9 VREFP VREFN XXXX XXXX VSS VDD_CORE 8 AIN2 AIN0 AIN4 VSSA_ADC VS...

Page 12: ...XXXX MII1_TX_EN XXXX MII1_TXD3 16 USB0_DRVVBUS VDDS_PLL_MPU XXXX VDD_CORE XXXX VDDS 15 VDDSHV4 VDDSHV4 VSS VDD_CORE VSS VDDSHV5 14 XXXX VDDSHV4 VSS XXXX VSS VDDSHV5 13 XXXX VDD_CORE VDD_CORE XXXX VDD_CORE VDD_CORE 12 VSS VDD_CORE VDD_CORE VSS VDD_CORE VDD_CORE 11 VDD_CORE VSS VSS VSS VSS VSS 10 XXXX VSS XXXX XXXX XXXX VSS 9 VDD_CORE VSS VSS VSS VSS VSS 8 VSS VDD_CORE VDD_CORE VSS VDD_CORE VDD_CORE...

Page 13: ...AIT0 XXXX GPMC_CSn2 GPMC_AD8 GPMC_AD7 14 XXXX VSS XXXX VDDS GPMC_AD6 GPMC_CSn1 GPMC_AD5 13 XXXX VSS VDDSHV1 GPMC_AD13 GPMC_AD12 GPMC_AD4 GPMC_AD3 12 VSS VSS VDDSHV1 GPMC_AD10 GPMC_AD11 GPMC_AD2 XTALOUT 11 VDD_CORE VDD_CORE VDDSHV1 XXXX XXXX VSS_OSC XTALIN 10 XXXX XXXX VSS VSS VDDS_OSC GPMC_ADVn_ALE GPMC_AD0 9 VDD_CORE VDD_CORE VDDSHV1 XXXX XXXX GPMC_AD1 GPMC_OEn_REn 8 VSS VSS VDDSHV1 VDDS_PLL_CORE...

Page 14: ...ntation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Terminal Configuration and Functions Copyright 2011 2016 Texas Instruments Incorporated 4 1 2 ZCZ Package Pin Maps Top View The pin maps that follow show the pin assignments on the ZCZ package in three sections left middle and right ...

Page 15: ... UART1_TXD UART0_RXD USB1_DRVVBUS 14 MCASP0_AHCLKX EMU1 EMU0 XDMA_EVENT_INTR1 VDDS VDDSHV6 13 MCASP0_ACLKX MCASP0_FSX MCASP0_FSR MCASP0_AXR1 VDDSHV6 VDD_MPU 12 TCK MCASP0_ACLKR MCASP0_AHCLKR MCASP0_AXR0 VDDSHV6 VDD_MPU 11 TDO TDI TMS CAP_VDD_SRAM_MPU VDDSHV6 VDD_MPU 10 WARMRSTn TRSTn CAP_VBB_MPU VDDS_SRAM_MPU_BB VDDSHV6 VDD_MPU 9 VREFN VREFP AIN7 CAP_VDD_SRAM_CORE VDDS_SRAM_CORE_BG VDDS 8 AIN6 AIN...

Page 16: ...COL MII1_TX_EN MII1_TXD1 MII1_RXD2 MII1_RXD0 15 MMC0_DAT1 VDDS_PLL_MPU MII1_RX_ER MII1_TXD2 MII1_RXD1 USB0_CE 14 VDDSHV6 VDDSHV4 VDDSHV4 VDDSHV5 VDDSHV5 VSSA_USB 13 VDD_MPU VDD_MPU VDD_MPU VDDS VSS VDD_CORE 12 VSS VSS VDD_CORE VDD_CORE VSS VSS 11 VSS VDD_CORE VSS VSS VSS VDD_CORE 10 VDD_CORE VSS VSS VSS VSS VSS 9 VSS VSS VSS VSS VDD_CORE VSS 8 VSS VSS VSS VDD_CORE VDD_CORE VSS 7 VDD_CORE VSS VSS V...

Page 17: ... GPMC_A5 14 VSSA_USB VDDS GPMC_A4 GPMC_A3 GPMC_A2 GPMC_A1 13 VDD_CORE VDDSHV3 GPMC_A0 GPMC_CSn3 GPMC_AD15 GPMC_AD14 12 VDD_CORE VDDSHV3 GPMC_AD13 GPMC_AD12 GPMC_AD11 GPMC_CLK 11 VSS VDDSHV2 VDDS_OSC GPMC_AD10 XTALOUT VSS_OSC 10 VSS VDDSHV2 VDDS_PLL_CORE_LCD GPMC_AD9 GPMC_AD8 XTALIN 9 VDD_CORE VDDS GPMC_AD6 GPMC_AD7 GPMC_CSn1 GPMC_CSn2 8 VDD_CORE VDDSHV1 GPMC_AD2 GPMC_AD3 GPMC_AD4 GPMC_AD5 7 VSS VD...

Page 18: ...he default mode Note The default mode is the mode at the release of the reset also see the RESET REL MODE column b Modes 1 to 7 are possible modes for alternate functions On each terminal some modes are effectively used for alternate functions while some modes are not used and do not correspond to a functional configuration 5 TYPE Signal direction I Input O Output I O Input and Output D Open drain...

Page 19: ...d 10 HYS Indicates if the input buffer is with hysteresis 11 BUFFER STRENGTH Drive strength of the associated output buffer 12 PULLUP OR PULLDOWN TYPE Denotes the presence of an internal pullup or pulldown resistor Pullup and pulldown resistors can be enabled or disabled via software 13 IO CELL IO cell information Note Configuring two terminals to the same input signal is not supported as it can y...

Page 20: ...DC VDDA_ADC NA NA NA Analog A12 C9 AIN7 AIN7 0 A Z Z 0 VDDA_ADC VDDA_ADC NA NA NA Analog C13 C10 CAP_VBB_MPU CAP_VBB_MPU NA A D6 D6 CAP_VDD_RTC CAP_VDD_RTC NA A B10 D9 CAP_VDD_SRAM_CORE CAP_VDD_SRAM_CORE NA A D13 D11 CAP_VDD_SRAM_MPU CAP_VDD_SRAM_MPU NA A F3 F3 DDR_A0 ddr_a0 0 O H 1 0 VDDS_DDR VDDS_DDR NA 8 PU PD LVCMOS SSTL HSTL J2 H1 DDR_A1 ddr_a1 0 O H 1 0 VDDS_DDR VDDS_DDR NA 8 PU PD LVCMOS SS...

Page 21: ...A 8 PU PD LVCMOS SSTL HSTL F1 F1 DDR_CASn ddr_casn 0 O H 1 0 VDDS_DDR VDDS_DDR NA 8 PU PD LVCMOS SSTL HSTL C2 D2 DDR_CK ddr_ck 0 O L 0 0 VDDS_DDR VDDS_DDR NA 8 PU PD LVCMOS SSTL HSTL G3 G3 DDR_CKE ddr_cke 0 O L 0 0 VDDS_DDR VDDS_DDR NA 8 PU PD LVCMOS SSTL HSTL C1 D1 DDR_CKn ddr_nck 0 O H 1 0 VDDS_DDR VDDS_DDR NA 8 PU PD LVCMOS SSTL HSTL H2 H2 DDR_CSn0 ddr_csn0 0 O H 1 0 VDDS_DDR VDDS_DDR NA 8 PU P...

Page 22: ... VDDS_DDR NA 8 PU PD LVCMOS SSTL HSTL K3 J2 DDR_DQM1 ddr_dqm1 0 O H 1 0 VDDS_DDR VDDS_DDR NA 8 PU PD LVCMOS SSTL HSTL R1 P1 DDR_DQS0 ddr_dqs0 0 I O L Z 0 VDDS_DDR VDDS_DDR Yes 8 PU PD LVCMOS SSTL HSTL L1 L1 DDR_DQS1 ddr_dqs1 0 I O L Z 0 VDDS_DDR VDDS_DDR Yes 8 PU PD LVCMOS SSTL HSTL R2 P2 DDR_DQSn0 ddr_dqsn0 0 I O H Z 0 VDDS_DDR VDDS_DDR Yes 8 PU PD LVCMOS SSTL HSTL L2 L2 DDR_DQSn1 ddr_dqsn1 0 I O...

Page 23: ...8 7 I O C17 B18 EXTINTn nNMI 0 I Z H 0 VDDSHV6 VDDSHV6 Yes NA PU PD LVCMOS B5 C5 EXT_WAKEUP EXT_WAKEUP 0 I L Z 0 VDDS_RTC VDDS_RTC Yes NA NA LVCMOS NA R13 GPMC_A0 gpmc_a0 0 O L L 7 NA VDDSHV3 Yes 6 PU PD LVCMOS gmii2_txen 1 O rgmii2_tctl 2 O rmii2_txen 3 O gpmc_a16 4 O pr1_mii_mt1_clk 5 I ehrpwm1_tripzone_input 6 I gpio1_16 7 I O NA V14 GPMC_A1 gpmc_a1 0 O L L 7 NA VDDSHV3 Yes 6 PU PD LVCMOS gmii2...

Page 24: ...GTH mA 11 PULLUP DOWN TYPE 12 I O CELL 13 NA R14 GPMC_A4 gpmc_a4 0 O L L 7 NA VDDSHV3 Yes 6 PU PD LVCMOS gmii2_txd1 1 O rgmii2_td1 2 O rmii2_txd1 3 O gpmc_a20 4 O pr1_mii1_txd0 5 O eQEP1A_in 6 I gpio1_20 7 I O NA V15 GPMC_A5 gpmc_a5 0 O L L 7 NA VDDSHV3 Yes 6 PU PD LVCMOS gmii2_txd0 1 O rgmii2_td0 2 O rmii2_txd0 3 O gpmc_a21 4 O pr1_mii1_rxd3 5 I eQEP1B_in 6 I gpio1_21 7 I O NA U15 GPMC_A6 gpmc_a6...

Page 25: ...3 1 I rgmii2_rd3 2 I mmc2_dat6 3 I O gpmc_a24 4 O pr1_mii1_rxd0 5 I mcasp0_aclkx 6 I O gpio1_24 7 I O NA U16 GPMC_A9 10 gpmc_a9 0 O L L 7 NA VDDSHV3 Yes 6 PU PD LVCMOS gmii2_rxd2 1 I rgmii2_rd2 2 I mmc2_dat7 rmii2_crs_dv 3 I O gpmc_a25 4 O pr1_mii_mr1_clk 5 I mcasp0_fsx 6 I O gpio1_25 7 I O NA T16 GPMC_A10 gpmc_a10 0 O L L 7 NA VDDSHV3 Yes 6 PU PD LVCMOS gmii2_rxd1 1 I rgmii2_rd1 2 I rmii2_rxd1 3 ...

Page 26: ... gpio1_2 7 I O W13 T8 GPMC_AD3 gpmc_ad3 0 I O L L 7 VDDSHV1 VDDSHV1 Yes 6 PU PD LVCMOS mmc1_dat3 1 I O gpio1_3 7 I O V13 U8 GPMC_AD4 gpmc_ad4 0 I O L L 7 VDDSHV1 VDDSHV1 Yes 6 PU PD LVCMOS mmc1_dat4 1 I O gpio1_4 7 I O W14 V8 GPMC_AD5 gpmc_ad5 0 I O L L 7 VDDSHV1 VDDSHV1 Yes 6 PU PD LVCMOS mmc1_dat5 1 I O gpio1_5 7 I O U14 R9 GPMC_AD6 gpmc_ad6 0 I O L L 7 VDDSHV1 VDDSHV1 Yes 6 PU PD LVCMOS mmc1_da...

Page 27: ...1 1 O mmc1_dat2 2 I O mmc2_dat6 3 I O ehrpwm2_tripzone_input 4 I pr1_mii0_txen 5 O gpio0_26 7 I O U12 U12 GPMC_AD11 gpmc_ad11 0 I O L L 7 VDDSHV1 VDDSHV2 Yes 6 PU PD LVCMOS lcd_data20 1 O mmc1_dat3 2 I O mmc2_dat7 3 I O ehrpwm0_synco 4 O pr1_mii0_txd3 5 O gpio0_27 7 I O U13 T12 GPMC_AD12 gpmc_ad12 0 I O L L 7 VDDSHV1 VDDSHV2 Yes 6 PU PD LVCMOS lcd_data19 1 O mmc1_dat4 2 I O mmc2_dat0 3 I O eQEP2A_...

Page 28: ...s 6 PU PD LVCMOS lcd_data16 1 O mmc1_dat7 2 I O mmc2_dat3 3 I O eQEP2_strobe 4 I O pr1_ecap0_ecap_capin_apwm_o 5 I O pr1_pru0_pru_r31_15 6 I gpio1_15 7 I O V10 R7 GPMC_ADVn_ALE gpmc_advn_ale 0 O H H 7 VDDSHV1 VDDSHV1 Yes 6 PU PD LVCMOS timer4 2 I O gpio2_2 7 I O V8 T6 GPMC_BEn0_CLE gpmc_be0n_cle 0 O H H 7 VDDSHV1 VDDSHV1 Yes 6 PU PD LVCMOS timer5 2 I O gpio2_5 7 I O V18 U18 GPMC_BEn1 gpmc_be1n 0 O...

Page 29: ..._edio_data_in6 3 I pr1_edio_data_out6 4 O pr1_pru1_pru_r30_12 5 O pr1_pru1_pru_r31_12 6 I gpio1_30 7 I O U15 V9 GPMC_CSn2 gpmc_csn2 0 O H H 7 VDDSHV1 VDDSHV1 Yes 6 PU PD LVCMOS gpmc_be1n 1 O mmc1_cmd 2 I O pr1_edio_data_in7 3 I pr1_edio_data_out7 4 O pr1_pru1_pru_r30_13 5 O pr1_pru1_pru_r31_13 6 I gpio1_31 7 I O U17 T13 GPMC_CSn3 6 gpmc_csn3 0 O H H 7 VDDSHV1 VDDSHV2 Yes 6 PU PD LVCMOS gpmc_a3 1 O...

Page 30: ... VDDSHV3 Yes 6 PU PD LVCMOS gmii2_rxerr 1 I gpmc_csn5 2 O rmii2_rxerr 3 I mmc2_sdcd 4 I pr1_mii1_txen 5 O uart4_txd 6 O gpio0_31 7 I O C18 C17 I2C0_SDA I2C0_SDA 0 I OD Z H 7 VDDSHV6 VDDSHV6 Yes 4 PU PD LVCMOS timer4 1 I O uart2_ctsn 2 I eCAP2_in_PWM2_out 3 I O gpio3_5 7 I O B19 C16 I2C0_SCL I2C0_SCL 0 I OD Z H 7 VDDSHV6 VDDSHV6 Yes 4 PU PD LVCMOS timer7 1 I O uart2_rtsn 2 O eCAP1_in_PWM1_out 3 I O...

Page 31: ...MOS gpmc_a1 1 O pr1_mii0_txen 2 O ehrpwm2B 3 O pr1_pru1_pru_r30_1 5 O pr1_pru1_pru_r31_1 6 I gpio2_7 7 I O V1 R3 LCD_DATA2 5 lcd_data2 0 I O Z Z 7 VDDSHV6 VDDSHV6 Yes 6 PU PD LVCMOS gpmc_a2 1 O pr1_mii0_txd3 2 O ehrpwm2_tripzone_input 3 I pr1_pru1_pru_r30_2 5 O pr1_pru1_pru_r31_2 6 I gpio2_8 7 I O V2 R4 LCD_DATA3 5 lcd_data3 0 I O Z Z 7 VDDSHV6 VDDSHV6 Yes 6 PU PD LVCMOS gpmc_a3 1 O pr1_mii0_txd2 ...

Page 32: ... lcd_data6 0 I O Z Z 7 VDDSHV6 VDDSHV6 Yes 6 PU PD LVCMOS gpmc_a6 1 O pr1_edio_data_in6 2 I eQEP2_index 3 I O pr1_edio_data_out6 4 O pr1_pru1_pru_r30_6 5 O pr1_pru1_pru_r31_6 6 I gpio2_12 7 I O U3 T4 LCD_DATA7 5 lcd_data7 0 I O Z Z 7 VDDSHV6 VDDSHV6 Yes 6 PU PD LVCMOS gpmc_a7 1 O pr1_edio_data_in7 2 I eQEP2_strobe 3 I O pr1_edio_data_out7 4 O pr1_pru1_pru_r30_7 5 O pr1_pru1_pru_r31_7 6 I gpio2_13 ...

Page 33: ...PE 12 I O CELL 13 U5 U3 LCD_DATA10 5 lcd_data10 0 I O Z Z 7 VDDSHV6 VDDSHV6 Yes 6 PU PD LVCMOS gpmc_a14 1 O ehrpwm1A 2 O mcasp0_axr0 3 I O pr1_mii0_rxd1 5 I uart3_ctsn 6 I gpio2_16 7 I O V5 U4 LCD_DATA11 5 lcd_data11 0 I O Z Z 7 VDDSHV6 VDDSHV6 Yes 6 PU PD LVCMOS gpmc_a15 1 O ehrpwm1B 2 O mcasp0_ahclkr 3 I O mcasp0_axr2 4 I O pr1_mii0_rxd0 5 I uart3_rtsn 6 O gpio2_17 7 I O V6 V2 LCD_DATA12 5 lcd_d...

Page 34: ...TA14 5 lcd_data14 0 I O Z Z 7 VDDSHV6 VDDSHV6 Yes 6 PU PD LVCMOS gpmc_a18 1 O eQEP1_index 2 I O mcasp0_axr1 3 I O uart5_rxd 4 I pr1_mii_mr0_clk 5 I uart5_ctsn 6 I gpio0_10 7 I O V7 T5 LCD_DATA15 5 lcd_data15 0 I O Z Z 7 VDDSHV6 VDDSHV6 Yes 6 PU PD LVCMOS gpmc_a19 1 O eQEP1_strobe 2 I O mcasp0_ahclkx 3 I O mcasp0_axr3 4 I O pr1_mii0_rxdv 5 I uart5_rtsn 6 O gpio0_11 7 I O T7 R5 LCD_HSYNC 7 lcd_hsync...

Page 35: ...VSYNC 7 lcd_vsync 0 O Z L 7 VDDSHV6 VDDSHV6 Yes 6 PU PD LVCMOS gpmc_a8 1 O gpmc_a1 2 O pr1_edio_data_in2 3 I pr1_edio_data_out2 4 O pr1_pru1_pru_r30_8 5 O pr1_pru1_pru_r31_8 6 I gpio2_22 7 I O NA B13 MCASP0_FSX mcasp0_fsx 0 I O L L 7 NA VDDSHV6 Yes 6 PU PD LVCMOS ehrpwm0B 1 O spi1_d0 3 I O mmc1_sdcd 4 I pr1_pru0_pru_r30_1 5 O pr1_pru0_pru_r31_1 6 I gpio3_15 7 I O NA B12 MCASP0_ACLKR mcasp0_aclkr 0...

Page 36: ...be 1 I O mcasp0_axr3 2 I O mcasp1_axr1 3 I O EMU4 4 I O pr1_pru0_pru_r30_7 5 O pr1_pru0_pru_r31_7 6 I gpio3_21 7 I O NA A13 MCASP0_ACLKX mcasp0_aclkx 0 I O L L 7 NA VDDSHV6 Yes 6 PU PD LVCMOS ehrpwm0A 1 O spi1_sclk 3 I O mmc0_sdcd 4 I pr1_pru0_pru_r30_0 5 O pr1_pru0_pru_r31_0 6 I gpio3_14 7 I O NA C13 MCASP0_FSR mcasp0_fsr 0 I O L L 7 NA VDDSHV6 Yes 6 PU PD LVCMOS eQEP0B_in 1 I mcasp0_axr3 2 I O m...

Page 37: ...LUP DOWN TYPE 12 I O CELL 13 R19 M18 MDC mdio_clk 0 O H H 7 VDDSHV5 VDDSHV5 Yes 6 PU PD LVCMOS timer5 1 I O uart5_txd 2 O uart3_rtsn 3 O mmc0_sdwp 4 I mmc1_clk 5 I O mmc2_clk 6 I O gpio0_1 7 I O P17 M17 MDIO mdio_data 0 I O H H 7 VDDSHV5 VDDSHV5 Yes 6 PU PD LVCMOS timer6 1 I O uart5_rxd 2 I uart3_ctsn 3 I mmc0_sdcd 4 I mmc1_cmd 5 I O mmc2_cmd 6 I O gpio0_0 7 I O L19 J17 MII1_RX_DV gmii1_rxdv 0 I L...

Page 38: ...2 I O CELL 13 K19 J15 MII1_RX_ER gmii1_rxerr 0 I L L 7 VDDSHV5 VDDSHV5 Yes 6 PU PD LVCMOS rmii1_rxerr 1 I spi1_d1 2 I O I2C1_SCL 3 I OD mcasp1_fsx 4 I O uart5_rtsn 5 O uart2_txd 6 O gpio3_2 7 I O M19 L18 MII1_RX_CLK gmii1_rxclk 0 I L L 7 VDDSHV5 VDDSHV5 Yes 6 PU PD LVCMOS uart2_txd 1 O rgmii1_rclk 2 I mmc0_dat6 3 I O mmc1_dat1 4 I O uart1_dsrn 5 I mcasp0_fsx 6 I O gpio3_10 7 I O N19 K18 MII1_TX_CL...

Page 39: ...I O CELL 13 J18 H17 MII1_CRS gmii1_crs 0 I L L 7 VDDSHV5 VDDSHV5 Yes 6 PU PD LVCMOS rmii1_crs_dv 1 I spi1_d0 2 I O I2C1_SDA 3 I OD mcasp1_aclkx 4 I O uart5_ctsn 5 I uart2_rxd 6 I gpio3_1 7 I O P18 M16 MII1_RXD0 gmii1_rxd0 0 I L L 7 VDDSHV5 VDDSHV5 Yes 6 PU PD LVCMOS rmii1_rxd0 1 I rgmii1_rd0 2 I mcasp1_ahclkx 3 I O mcasp1_ahclkr 4 I O mcasp1_aclkr 5 I O mcasp0_axr3 6 I O gpio2_21 7 I O P19 L15 MII...

Page 40: ...E 12 I O CELL 13 N17 L17 MII1_RXD3 gmii1_rxd3 0 I L L 7 VDDSHV5 VDDSHV5 Yes 6 PU PD LVCMOS uart3_rxd 1 I rgmii1_rd3 2 I mmc0_dat5 3 I O mmc1_dat2 4 I O uart1_dtrn 5 O mcasp0_axr0 6 I O gpio2_18 7 I O L18 K17 MII1_TXD0 gmii1_txd0 0 O L L 7 VDDSHV5 VDDSHV5 Yes 6 PU PD LVCMOS rmii1_txd0 1 O rgmii1_td0 2 O mcasp1_axr2 3 I O mcasp1_aclkr 4 I O eQEP0B_in 5 I mmc1_clk 6 I O gpio0_28 7 I O M18 K16 MII1_TX...

Page 41: ...ELL 13 M17 J18 MII1_TXD3 gmii1_txd3 0 O L L 7 VDDSHV5 VDDSHV5 Yes 6 PU PD LVCMOS dcan0_tx 1 O rgmii1_td3 2 O uart4_rxd 3 I mcasp1_fsx 4 I O mmc2_dat1 5 I O mcasp0_fsr 6 I O gpio0_16 7 I O G17 G18 MMC0_CMD mmc0_cmd 0 I O H H 7 VDDSHV4 VDDSHV4 Yes 6 PU PD LVCMOS gpmc_a25 1 O uart3_rtsn 2 O uart2_txd 3 O dcan1_rx 4 I pr1_pru0_pru_r30_13 5 O pr1_pru0_pru_r31_13 6 I gpio2_31 7 I O G19 G17 MMC0_CLK mmc0...

Page 42: ... 5 O pr1_pru0_pru_r31_10 6 I gpio2_28 7 I O H18 F18 MMC0_DAT2 mmc0_dat2 0 I O H H 7 VDDSHV4 VDDSHV4 Yes 6 PU PD LVCMOS gpmc_a21 1 O uart4_rtsn 2 O timer6 3 I O uart1_dsrn 4 I pr1_pru0_pru_r30_9 5 O pr1_pru0_pru_r31_9 6 I gpio2_27 7 I O H19 F17 MMC0_DAT3 mmc0_dat3 0 I O H H 7 VDDSHV4 VDDSHV4 Yes 6 PU PD LVCMOS gpmc_a20 1 O uart4_ctsn 2 I timer5 3 I O uart1_dcdn 4 I pr1_pru0_pru_r30_8 5 O pr1_pru0_p...

Page 43: ...0 I H H 0 VDDS_RTC VDDS_RTC Yes NA PU 1 LVCMOS A5 A4 RTC_XTALOUT OSC1_OUT 0 O Z 23 Z 23 0 VDDS_RTC VDDS_RTC NA NA 15 NA LVCMOS A18 A17 SPI0_SCLK spi0_sclk 0 I O Z H 7 VDDSHV6 VDDSHV6 Yes 6 PU PD LVCMOS uart2_rxd 1 I I2C2_SDA 2 I OD ehrpwm0A 3 O pr1_uart0_cts_n 4 I pr1_edio_sof 5 O EMU2 6 I O gpio0_2 7 I O A17 A16 SPI0_CS0 spi0_cs0 0 I O Z H 7 VDDSHV6 VDDSHV6 Yes 6 PU PD LVCMOS mmc2_sdwp 1 I I2C1_S...

Page 44: ...CMOS mmc1_sdwp 1 I I2C1_SDA 2 I OD ehrpwm0_tripzone_input 3 I pr1_uart0_rxd 4 I pr1_edio_data_in0 5 I pr1_edio_data_out0 6 O gpio0_4 7 I O B14 A12 TCK TCK 0 I H H 0 VDDSHV6 VDDSHV6 Yes NA PU PD LVCMOS B13 B11 TDI TDI 0 I H H 0 VDDSHV6 VDDSHV6 Yes NA PU PD LVCMOS A14 A11 TDO TDO 0 O H H 0 VDDSHV6 VDDSHV6 NA 4 PU PD LVCMOS C14 C11 TMS TMS 0 I H H 0 VDDSHV6 VDDSHV6 Yes NA PU PD LVCMOS A13 B10 TRSTn n...

Page 45: ...1_cs0 1 I O dcan0_tx 2 O I2C2_SDA 3 I OD eCAP2_in_PWM2_out 4 I O pr1_pru1_pru_r30_14 5 O pr1_pru1_pru_r31_14 6 I gpio1_10 7 I O F18 E17 UART0_RTSn uart0_rtsn 0 O Z H 7 VDDSHV6 VDDSHV6 Yes 4 PU PD LVCMOS uart4_txd 1 O dcan1_rx 2 I I2C1_SCL 3 I OD spi1_d1 4 I O spi1_cs0 5 I O pr1_edc_sync1_out 6 O gpio1_9 7 I O C19 D15 UART1_TXD uart1_txd 0 O Z H 7 VDDSHV6 VDDSHV6 Yes 4 PU PD LVCMOS mmc2_sdwp 1 I dc...

Page 46: ... T19 P15 USB0_VBUS USB0_VBUS 0 A Z Z 0 VDDA _USB0 VDDA _USB0 26 NA NA NA Analog U18 N18 USB0_DM USB0_DM 0 A Z Z 0 13 VDDA _USB0 VDDA _USB0 26 Yes 16 8 16 NA Analog G16 F16 USB0_DRVVBUS USB0_DRVVBUS 0 O L 0 PD 0 VDDSHV6 VDDSHV6 Yes 4 PU PD LVCMOS gpio0_18 7 I O V19 P16 USB0_ID USB0_ID 0 A Z Z 0 VDDA _USB0 VDDA _USB0 26 NA NA NA Analog U19 N17 USB0_DP USB0_DP 0 A Z Z 0 13 VDDA _USB0 VDDA _USB0 26 Ye...

Page 47: ...HV3 NA PWR G15 H14 H15 H14 J14 VDDSHV4 VDDSHV4 NA PWR M14 M15 N15 K14 L14 VDDSHV5 VDDSHV5 NA PWR E11 E12 E13 F14 P6 R7 E10 E11 E12 E13 F14 G14 N5 P5 P6 VDDSHV6 VDDSHV6 NA PWR G5 H5 H6 K4 K5 M5 M6 N5 E5 F5 G5 H5 J5 K5 L5 VDDS_DDR VDDS_DDR NA PWR U10 R11 VDDS_OSC VDDS_OSC NA PWR T8 R10 VDDS_PLL_CORE_LCD VDDS_PLL_CORE_LCD NA PWR C5 E7 VDDS_PLL_DDR VDDS_PLL_DDR NA PWR H16 H15 VDDS_PLL_MPU VDDS_PLL_MPU...

Page 48: ...N8 N12 P7 P8 P12 P13 P14 R10 T10 W1 W19 A1 A18 F8 G8 G9 G11 G12 H6 H7 H8 H9 H10 H12 J6 J7 J8 J9 J10 J11 K7 K9 K10 K11 L10 L11 L12 L13 M6 M7 M8 M9 M10 M12 N7 N10 N11 V1 V18 VSS VSS NA GND D8 E8 VSSA_ADC VSSA_ADC NA GND P16 M14 N14 VSSA_USB VSSA_USB NA GND V11 V11 VSS_OSC VSS_OSC 28 NA A NA A5 VSS_RTC VSS_RTC 29 NA A A16 A10 WARMRSTn nRESETIN_OUT 0 I OD 8 0 0 PU 11 0 VDDSHV6 VDDSHV6 Yes 4 PU PD LVCM...

Page 49: ...X signals to this terminal For more details refer to USB GPIO Details section of the AM335x Technical Reference Manual 14 The internal USB PHY can be configured to multiplex the UART3_TX or UART3_RX signals to this terminal For more details refer to USB GPIO Details section of the AM335x Technical Reference Manual 15 This output should only be used to source the recommended crystal circuit 16 This...

Page 50: ...ck Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 50 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 SPRS717J OCTOBER 2011 REVISED APRIL 2016 www ti com PCB power distribution network and package When the Kelvin connection is not used it should be connected to the same power source as VDD_MPU ...

Page 51: ...iplex up to eight signal functions Although there are many combinations of pin multiplexing that are possible only a certain number of sets called IO Sets are valid due to timing limitations These valid IO Sets were carefully chosen to provide many possible application scenarios for the user Texas Instruments has developed a Windows based application called Pin Mux Utility that helps a system desi...

Page 52: ...egative Reference Input AP B9 A9 VREFP Analog Positive Reference Input AP A9 B9 Debug Subsystem Signals Description SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 EMU0 MISC EMULATION PIN I O A15 C14 EMU1 MISC EMULATION PIN I O D14 B14 EMU2 MISC EMULATION PIN I O A18 C15 A15 A17 C13 EMU3 MISC EMULATION PIN I O B15 B18 B17 D13 D14 EMU4 MISC EMULATION PIN I O B16 U17 A14 C15 T13 nTRST JTAG ...

Page 53: ... LCD data bus O T13 R12 lcd_data19 LCD data bus O U13 T12 lcd_data2 LCD data bus I O V1 R3 lcd_data20 LCD data bus O U12 U12 lcd_data21 LCD data bus O T12 T11 lcd_data22 LCD data bus O W16 T10 lcd_data23 LCD data bus O V15 U10 lcd_data3 LCD data bus I O V2 R4 lcd_data4 LCD data bus I O W2 T1 lcd_data5 LCD data bus I O W3 T2 lcd_data6 LCD data bus I O V3 T3 lcd_data7 LCD data bus I O U3 T4 lcd_data...

Page 54: ...4 DDR SDRAM ROW COLUMN ADDRESS OUTPUT O E5 C2 ddr_a5 DDR SDRAM ROW COLUMN ADDRESS OUTPUT O A2 B1 ddr_a6 DDR SDRAM ROW COLUMN ADDRESS OUTPUT O B1 D5 ddr_a7 DDR SDRAM ROW COLUMN ADDRESS OUTPUT O D2 E2 ddr_a8 DDR SDRAM ROW COLUMN ADDRESS OUTPUT O C3 D4 ddr_a9 DDR SDRAM ROW COLUMN ADDRESS OUTPUT O B2 C1 ddr_ba0 DDR SDRAM BANK ADDRESS OUTPUT O A3 C4 ddr_ba1 DDR SDRAM BANK ADDRESS OUTPUT O E1 E1 ddr_ba2...

Page 55: ...ifferential I O L2 L2 ddr_nck DDR SDRAM CLOCK OUTPUT Differential O C1 D1 ddr_odt ODT OUTPUT O G1 G1 ddr_rasn DDR SDRAM ROW ADDRESS STROBE OUTPUT ACTIVE LOW O F2 G4 ddr_resetn DDR3 DDR3L RESET OUTPUT ACTIVE LOW O G2 G2 ddr_vref Voltage Reference Input A H4 J4 ddr_vtp VTP Compensation Resistor I J1 J3 ddr_wen DDR SDRAM WRITE ENABLE OUTPUT ACTIVE LOW O A4 B2 External Memory Interfaces General Purpos...

Page 56: ...Address and Data I O T13 R12 gpmc_ad14 GPMC Address and Data I O W17 V13 gpmc_ad15 GPMC Address and Data I O V17 U13 gpmc_ad2 GPMC Address and Data I O V12 R8 gpmc_ad3 GPMC Address and Data I O W13 T8 gpmc_ad4 GPMC Address and Data I O V13 U8 gpmc_ad5 GPMC Address and Data I O W14 V8 gpmc_ad6 GPMC Address and Data I O U14 R9 gpmc_ad7 GPMC Address and Data I O W15 T9 gpmc_ad8 GPMC Address and Data ...

Page 57: ... F16 gpio0_19 GPIO I O C15 A15 gpio0_2 GPIO I O A18 A17 gpio0_20 GPIO I O B15 D14 gpio0_21 GPIO I O M18 K16 gpio0_22 GPIO I O V15 U10 gpio0_23 GPIO I O W16 T10 gpio0_26 GPIO I O T12 T11 gpio0_27 GPIO I O U12 U12 gpio0_28 GPIO I O L18 K17 gpio0_29 GPIO I O K18 H18 gpio0_3 GPIO I O B18 B17 gpio0_30 GPIO I O R15 T17 gpio0_31 GPIO I O W18 U17 gpio0_4 GPIO I O B17 B16 gpio0_5 GPIO I O A17 A16 gpio0_6 G...

Page 58: ...3 GPIO I O W13 T8 gpio1_30 GPIO I O V14 U9 gpio1_31 GPIO I O U15 V9 gpio1_4 GPIO I O V13 U8 gpio1_5 GPIO I O W14 V8 gpio1_6 GPIO I O U14 R9 gpio1_7 GPIO I O W15 T9 gpio1_8 GPIO I O F19 E18 gpio1_9 GPIO I O F18 E17 General Purpose IOs GPIO2 Signals Description SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 gpio2_0 GPIO I O U17 T13 gpio2_1 GPIO I O V16 V12 gpio2_10 GPIO I O W2 T1 gpio2_11 ...

Page 59: ... GPIO I O V8 T6 gpio2_6 GPIO I O U1 R1 gpio2_7 GPIO I O U2 R2 gpio2_8 GPIO I O V1 R3 gpio2_9 GPIO I O V2 R4 General Purpose IOs GPIO3 Signals Description SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 gpio3_0 GPIO I O J19 H16 gpio3_1 GPIO I O J18 H17 gpio3_10 GPIO I O M19 L18 gpio3_13 GPIO I O NA F15 gpio3_14 GPIO I O NA A13 gpio3_15 GPIO I O NA B13 gpio3_16 GPIO I O NA D12 gpio3_17 GPIO...

Page 60: ...7 B4 EXT_WAKEUP EXT_WAKEUP input I B5 C5 nNMI External Interrupt to ARM Cortex A8 core I C17 B18 nRESETIN_OUT Active low Warm Reset I OD A16 A10 OSC0_IN High frequency oscillator input I W11 V10 OSC0_OUT High frequency oscillator output O W12 U11 OSC1_IN Low frequency 32 768 kHz Real Time Clock oscillator input I A6 A6 OSC1_OUT Low frequency 32 768 kHz Real Time Clock oscillator output O A5 A4 PMI...

Page 61: ...ls Description SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 eCAP0_in_PWM0_out Enhanced Capture 0 input or Auxiliary PWM0 output I O E18 C18 eCAP eCAP1 Signals Description SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 eCAP1_in_PWM1_out Enhanced Capture 1 input or Auxiliary PWM1 output I O B16 B19 F17 C15 C16 E16 eCAP eCAP2 Signals Description SIGNAL NAME 1 DESCRIPTION 2 TYPE ...

Page 62: ...ci Sync input to eHRPWM0 module from an external pin I A17 A16 C12 ehrpwm0_synco Sync Output from eHRPWM0 module to an external pin O U12 V2 W4 R4 U12 U2 V14 ehrpwm0_tripzone_input eHRPWM0 trip zone input I B17 B16 D12 eHRPWM eHRPWM1 Signals Description SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 ehrpwm1A eHRPWM1 A output O U5 U14 U3 ehrpwm1B eHRPWM1 B output O V5 T14 U4 ehrpwm1_tripz...

Page 63: ...P0B quadrature input I L18 C13 K17 eQEP0_index eQEP0 index I O K17 D13 J16 eQEP0_strobe eQEP0 strobe I O P19 A14 L15 eQEP eQEP1 Signals Description SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 eQEP1A_in eQEP1A quadrature input I V6 R14 V2 eQEP1B_in eQEP1B quadrature input I U6 V15 V3 eQEP1_index eQEP1 index I O W6 U15 V4 eQEP1_strobe eQEP1 strobe I O V7 T15 T5 eQEP eQEP2 Signals Descri...

Page 64: ...ZCE BALL 4 ZCZ BALL 4 timer4 Timer trigger event PWM out I O C15 C18 K17 V10 A15 C17 J16 R7 Timer Timer5 Signals Description SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 timer5 Timer trigger event PWM out I O D19 H19 R19 V8 D17 F17 M18 T6 Timer Timer6 Signals Description SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 timer6 Timer trigger event PWM out I O E17 H18 P17 U8 D18 F...

Page 65: ... W7 R6 pr1_edio_data_in6 Data In I V14 V3 T3 U9 pr1_edio_data_in7 Data In I U15 U3 T4 V9 pr1_edio_data_out0 Data Out O B17 B16 pr1_edio_data_out1 Data Out O A17 A16 pr1_edio_data_out2 Data Out O U7 U5 pr1_edio_data_out3 Data Out O T7 R5 pr1_edio_data_out4 Data Out O W5 V5 pr1_edio_data_out5 Data Out O W7 R6 pr1_edio_data_out6 Data Out O V14 V3 T3 U9 pr1_edio_data_out7 Data Out O U15 U3 T4 V9 pr1_e...

Page 66: ... BALL 4 pr1_mii1_col MII Collision Detect I R15 T17 pr1_mii1_crs MII Carrier Sense I V16 W7 R6 V12 pr1_mii1_rxd0 MII Receive Data bit 0 I NA V16 pr1_mii1_rxd1 MII Receive Data bit 1 I NA T15 pr1_mii1_rxd2 MII Receive Data bit 2 I NA U15 pr1_mii1_rxd3 MII Receive Data bit 3 I NA V15 pr1_mii1_rxdv MII Receive Data Valid I NA T16 pr1_mii1_rxer MII Receive Data Error I NA V17 pr1_mii1_rxlink MII Recei...

Page 67: ...1_3 PRU0 Data In I NA C12 pr1_pru0_pru_r31_4 PRU0 Data In I NA B12 pr1_pru0_pru_r31_5 PRU0 Data In I NA C13 pr1_pru0_pru_r31_6 PRU0 Data In I NA D13 pr1_pru0_pru_r31_7 PRU0 Data In I NA A14 pr1_pru0_pru_r31_8 PRU0 Data In I H19 F17 pr1_pru0_pru_r31_9 PRU0 Data In I H18 F18 PRU0 General Purpose Outputs Signals Description SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 pr1_pru0_pru_r30_0 P...

Page 68: ...u1_pru_r31_3 PRU1 Data In I V2 R4 pr1_pru1_pru_r31_4 PRU1 Data In I W2 T1 pr1_pru1_pru_r31_5 PRU1 Data In I W3 T2 pr1_pru1_pru_r31_6 PRU1 Data In I V3 T3 pr1_pru1_pru_r31_7 PRU1 Data In I U3 T4 pr1_pru1_pru_r31_8 PRU1 Data In I U7 U5 pr1_pru1_pru_r31_9 PRU1 Data In I T7 R5 PRU1 General Purpose Outputs Signals Description SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 pr1_pru1_pru_r30_0 P...

Page 69: ... SD SDIO Clock I O L18 R19 V14 K17 M18 U9 mmc1_cmd MMC SD SDIO Command I O M18 P17 U15 K16 M17 V9 mmc1_dat0 MMC SD SDIO Data Bus I O N19 V15 W10 K18 U10 U7 mmc1_dat1 MMC SD SDIO Data Bus I O M19 V9 W16 L18 T10 V7 mmc1_dat2 MMC SD SDIO Data Bus I O N17 T12 V12 L17 R8 T11 mmc1_dat3 MMC SD SDIO Data Bus I O N16 U12 W13 L16 T8 U12 mmc1_dat4 MMC SD SDIO Data Bus I O U13 V13 T12 U8 mmc1_dat5 MMC SD SDIO...

Page 70: ...6 Texas Instruments Incorporated Serial Communication Interfaces CAN CAN DCAN0 Signals Description SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 dcan0_rx DCAN0 Receive Data I D19 F17 N18 D17 E16 K15 dcan0_tx DCAN0 Transmit Data O E17 E19 M17 D18 E15 J18 CAN DCAN1 Signals Description SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 dcan1_rx DCAN1 Receive Data I C19 F18 G17 D15 E1...

Page 71: ...ransmit Clock I N19 K18 gmii1_txd0 MII Transmit Data bit 0 O L18 K17 gmii1_txd1 MII Transmit Data bit 1 O M18 K16 gmii1_txd2 MII Transmit Data bit 2 O N18 K15 gmii1_txd3 MII Transmit Data bit 3 O M17 J18 gmii1_txen MII Transmit Enable O K17 J16 GEMAC_CPSW MII2 Signals Description SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 gmii2_col MII Colision I V18 U18 gmii2_crs MII Carrier Sense I...

Page 72: ...ata bit 0 I NA V17 rgmii2_rd1 RGMII Receive Data bit 1 I NA T16 rgmii2_rd2 RGMII Receive Data bit 2 I NA U16 rgmii2_rd3 RGMII Receive Data bit 3 I NA V16 rgmii2_tclk RGMII Transmit Clock O NA U15 rgmii2_tctl RGMII Transmit Control O NA R13 rgmii2_td0 RGMII Transmit Data bit 0 O NA V15 rgmii2_td1 RGMII Transmit Data bit 1 O NA R14 rgmii2_td2 RGMII Transmit Data bit 2 O NA T14 rgmii2_td3 RGMII Trans...

Page 73: ...t Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Terminal Configuration and Functions Copyright 2011 2016 Texas Instruments Incorporated GEMAC_CPSW RMII2 Signals Description continued SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 rmii2_txd1 RMII Transmit Data bit 1 O NA R14 rmii2_txen RMII Transmit Enable O NA R13 ...

Page 74: ...Description SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 I2C0_SCL I2C0 Clock I OD B19 C16 I2C0_SDA I2C0 Data I OD C18 C17 I2C I2C1 Signals Description SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 I2C1_SCL I2C1 Clock I OD A17 C19 F18 K19 A16 D15 E17 J15 I2C1_SDA I2C1 Data I OD B17 D18 F19 J18 B16 D16 E18 H17 I2C I2C2 Signals Description SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE...

Page 75: ...L16 V17 V4 mcasp0_axr2 McASP0 Serial Data IN OUT I O J19 V5 V6 B12 C12 H16 U4 V2 mcasp0_axr3 McASP0 Serial Data IN OUT I O P18 U6 V7 A14 C13 M16 T5 V3 mcasp0_fsr McASP0 Receive Frame Sync I O M17 U6 V16 C13 J18 V12 V3 mcasp0_fsx McASP0 Transmit Frame Sync I O M19 W4 B13 L18 U16 U2 McASP MCASP1 Signals Description SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 mcasp1_aclkr McASP1 Receive ...

Page 76: ...SCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 spi0_cs0 SPI Chip Select I O A17 A16 spi0_cs1 SPI Chip Select I O B16 C15 spi0_d0 SPI Data I O B18 B17 spi0_d1 SPI Data I O B17 B16 spi0_sclk SPI Clock I O A18 A17 SPI SPI1 Signals Description SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 spi1_cs0 SPI Chip Select I O E17 E19 F18 K18 C12 D18 E15 E17 H18 spi1_cs1 SPI Chip Select I O C15 D19 E18 F17...

Page 77: ... D18 D16 uart1_txd UART Transmit Data O C19 D15 UART UART2 Signals Description SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 uart2_ctsn UART Clear to Send I C18 V4 C17 U1 uart2_rtsn UART Request to Send O B19 W4 C16 U2 uart2_rxd UART Receive Data I A18 G19 J18 N19 A17 G17 H17 K18 uart2_txd UART Transmit Data O B18 G17 K19 M19 B17 G18 J15 L18 UART UART3 Signals Description SIGNAL NAME 1 ...

Page 78: ...s AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Terminal Configuration and Functions Copyright 2011 2016 Texas Instruments Incorporated UART UART5 Signals Description continued SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 uart5_rxd UART Receive Data I J19 P17 W4 W6 H16 M17 U2 V4 uart5_txd UART Transmit Data O K18 L19 R19 V4 H18 J17 M18 U1 ...

Page 79: ...ive high Charger Enable output A T18 M15 USB0_DM USB0 Data minus A U18 N18 USB0_DP USB0 Data plus A U19 N17 USB0_DRVVBUS USB0 Active high VBUS control output O G16 F16 USB0_ID USB0 OTG ID Micro A or Micro B Plug A V19 P16 USB0_VBUS USB0 VBUS A T19 P15 USB USB1 Signals Description SIGNAL NAME 1 DESCRIPTION 2 TYPE 3 ZCE BALL 4 ZCZ BALL 4 USB1_CE USB1 Active high Charger Enable output A NA P18 USB1_D...

Page 80: ...US comparator input 0 5 5 25 V USB1_VBUS 6 7 Supply voltage for USB VBUS comparator input 0 5 5 25 V DDR_VREF Supply voltage for the DDR SSTL and HSTL reference voltage 0 3 1 1 V Steady state max voltage at all IO pins 8 0 5 V to IO supply voltage 0 3 V USB0_ID 9 Steady state maximum voltage for the USB ID input 0 5 2 1 V USB1_ID 6 9 Steady state maximum voltage for the USB ID input 0 5 2 1 V Tran...

Page 81: ...to ground for USB host operation or open circuit for USB peripheral operation and should never be connected to any external voltage source 10 Based on JEDEC JESD78D IC Latch Up Test 11 For tape and reel the storage temperature range is 10 C 50 C with a maximum relative humidity of 70 TI recommends returning to ambient room temperature before usage Fail safe IO terminals are designed such they do n...

Page 82: ...nge specified in the recommended operating conditions 4 The previous notations cannot be deemed a warranty or deemed to extend or modify the warranty under TI s standard terms and conditions for TI semiconductor products 5 POH Power on hours when the device is fully functional 5 4 Operating Performance Points OPPs Device OPPs are defined in Table 5 2 through Table 5 9 Table 5 2 VDD_CORE OPPs for Z...

Page 83: ...s two times the maximum memory clock frequency defined in this table Table 5 6 VDD_CORE OPPs for ZCZ Package with Device Revision Code A or Newer 1 VDD_CORE OPP Rev A or Newer VDD_CORE DDR3 DDR3L 2 DDR2 2 mDDR 2 L3 and L4 MIN NOM MAX OPP100 1 056 V 1 100 V 1 144 V 400 MHz 266 MHz 200 MHz 200 and 100 MHz OPP50 0 912 V 0 950 V 0 988 V 125 MHz 90 MHz 100 and 50 MHz 1 Frequencies in this table indicat...

Page 84: ...ge with Device Revision Code A or Newer 1 VDD_CORE OPP Rev A or newer VDD_MPU 2 ARM A8 DDR3 DDR3L 3 DDR2 3 mDDR 3 L3 and L4 MIN NOM MAX OPP100 1 056 V 1 100 V 1 144 V 600 MHz 400 MHz 266 MHz 200 MHz 200 and 100 MHz OPP100 1 056 V 1 100 V 1 144 V 300 MHz 400 MHz 266 MHz 200 MHz 200 and 100 MHz OPP50 0 912 V 0 950 V 0 988 V 300 MHz 125 MHz 90 MHz 100 and 50 MHz 1 Frequencies in this table indicate m...

Page 85: ...oltage range for DDR IO domain DDR3 1 425 1 500 1 575 Supply voltage range for DDR IO domain DDR3L 1 283 1 350 1 418 VDDS 4 Supply voltage range for all dual voltage IO domains 1 710 1 800 1 890 V VDDS_SRAM_CORE_BG Supply voltage range for Core SRAM LDOs analog 1 710 1 800 1 890 V VDDS_SRAM_MPU_BB Supply voltage range for MPU SRAM LDOs analog 1 710 1 800 1 890 V VDDS_PLL_DDR 5 Supply voltage range...

Page 86: ... 3 3 V operation 3 135 3 300 3 465 V DDR_VREF Voltage range for DDR SSTL and HSTL reference input DDR2 DDR3 DDR3L 0 49 VDDS_DDR 0 50 VDDS_DDR 0 51 VDDS_DDR V USB0_VBUS Voltage range for USB VBUS comparator input 0 000 5 000 5 250 V USB1_VBUS 6 Voltage range for USB VBUS comparator input 0 000 5 000 5 250 V USB0_ID Voltage range for the USB ID input 7 V USB1_ID 6 Voltage range for the USB ID input ...

Page 87: ...DPLL DDR 10 mA VDDS_PLL_CORE_LCD Maximum current rating for the DPLL Core and LCD 20 mA VDDS_PLL_MPU Maximum current rating for the DPLL MPU 10 mA VDDS_OSC Maximum current rating for the system oscillator IOs 5 mA VDDA1P8V_USB0 Maximum current rating for USBPHY 1 8 V 25 mA VDDA1P8V_USB1 4 Maximum current rating for USBPHY 1 8 V 25 mA VDDA3P3V_USB0 Maximum current rating for USBPHY 3 3 V 40 mA VDDA...

Page 88: ...ON PD_MPU OFF PD_GFX OFF PD_WKUP ON DDR is in self refresh 16 5 22 0 mW Deepsleep1 On chip peripheral registers are preserved Cortex A8 context registers are lost so the application needs to save them to the L3 OCMC RAM or DDR before entering DeepSleep DDR is in self refresh For wake up boot ROM executes and branches to system resume Power supplies All power supplies are ON VDD_MPU 0 95 V nom VDD_...

Page 89: ...DDR_RASn DDR_WEn DDR_BA0 DDR_BA1 DDR_BA2 DDR_A0 DDR_A1 DDR_A 2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14 DDR_A15 DDR_ODT DDR_D0 DD R_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 DDR_DQM 0 DDR_DQM1 DDR_DQS0 DDR_DQSn0 DDR_DQS1 DDR_DQSn1 Pins DDR2 SSTL Mode VIH High level input voltage DDR_VRE...

Page 90: ...ldown is inhibited 8 µA ECAP0_IN_PWM0_OUT UART0_CTSn UART0_RTSn UART0_RXD UART0_TXD UART1_CTSn UART1_RTSn UART1_RXD UART1_TXD I2C0_SDA I2C0_ SCL XDMA_EVENT_INTR0 XDMA_EVENT_INTR1 WARMRSTn EXTINTn TMS TDO USB0_DRVVBUS USB1_DRVVBUS VDDSHV6 3 3 V VIH High level input voltage 2 V VIL Low level input voltage 0 8 V VHYS Hysteresis voltage at an input 0 265 0 44 V VOH High level output voltage driver ena...

Page 91: ...ge 0 65 VDDS_RTC V VIL Low level input voltage 0 35 VDDS_RTC V VHYS Hysteresis voltage at an input 0 15 V II Input leakage current Receiver disabled pullup or pulldown inhibited 1 1 µA Input leakage current Receiver disabled pullup enabled 200 40 Input leakage current Receiver disabled pulldown enabled 40 200 XTALIN OSC0 VIH High level input voltage 0 65 VDDS_OSC V VIL Low level input voltage 0 35...

Page 92: ...N NOM MAX UNIT VOH High level output voltage driver enabled pullup or pulldown disabled IOH 6 mA VDDSHVx 0 45 V VOL Low level output voltage driver enabled pullup or pulldown disabled IOL 6 mA 0 45 V II Input leakage current Receiver disabled pullup or pulldown inhibited 18 µA Input leakage current Receiver disabled pullup enabled 243 100 19 Input leakage current Receiver disabled pulldown enabled...

Page 93: ...ce Characteristics for ZCE and ZCZ Packages Failure to maintain a junction temperature within the range specified in Section 5 5 reduces operating lifetime reliability and performance and may cause irreversible damage to the system Therefore the product design cycle should include thermal analysis to verify the maximum operating junction temperature of the device It is important this thermal analy...

Page 94: ... capacitor is most effective when located close to the AM335x device because this minimizes the inductance of the circuit board wiring and interconnects Table 5 13 Core Voltage Decoupling Characteristics PARAMETER TYP UNIT CVDD_CORE 1 10 08 μF CVDD_MPU 2 3 10 05 μF 1 The typical value corresponds to 1 cap of 10 μF and 8 caps of 10 nF 2 Not available on the ZCE package VDD_MPU is merged with VDD_CO...

Page 95: ...traces possible to minimize the voltage drop on VDDS_SRAM_CORE_BG terminals 5 VDDS_SRAM_MPU_BB supply powers an internal LDO for SRAM supplies Inrush currents could cause voltage drop on the VDDS_SRAM_MPU_BB supplies when the SRAM LDO is enabled after powering up VDDS_SRAM_MPU_BB terminals A 10 µF is recommended to be placed close to the terminal and routed with widest traces possible to minimize ...

Page 96: ..._1P8V_USBx CVDDA_1P8V_USBx VSSA_USB ADC VDDA_ADC CVDDA_ADC VSSA_ADC VDDS_OSC CVDDS_OSC RTC CAP_VDD_RTC CCAP_VDD_RTC VDDSHV1 IOs CVDDSHV1 96 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 SPRS717J OCTOBER 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Specifications Copyright 2011 2016 Texas Instruments Incorp...

Page 97: ...1 0 5 VDDA_ADC 0 25 VDDA_ADC V VREFN 1 0 0 5 VDDA_ADC 0 25 V VREFP VREFN 1 VDDA_ADC V Full scale input range Internal voltage reference 0 VDDA_ADC V External voltage reference VREFN VREFP Differential non linearity DNL Internal voltage reference VDDA_ADC 1 8 V External voltage reference VREFP VREFN 1 8 V 1 0 5 1 LSB Integral non linearity INL Source impedance 50 Ω Internal voltage reference VDDA_A...

Page 98: ...DC 1 8 V External voltage reference VREFP VREFN 1 8 V Input signal 30 kHz sine wave at 0 5 dB full scale 69 dB VREFP and VREFN input impedance 20 kΩ Input impedance of AIN 7 0 2 ƒ Input frequency 1 65 97 10 12 ƒ Ω Sampling Dynamics Conversion time 15 ADC clock cycles Acquisition time 2 ADC clock cycles Sampling rate ADC clock 3 MHz 200 kSPS Channel to channel isolation 100 dB Touch Screen Switch D...

Page 99: ...wer and Clocking Copyright 2011 2016 Texas Instruments Incorporated 6 Power and Clocking 6 1 Power Supplies 6 1 1 Power Supply Slew Rate Requirement To maintain the safe operating range of the internal ESD protection devices TI recommends limiting the maximum slew rate for powering on the supplies to be less than 1 0E 5 V s For instance as shown in Figure 6 1 TI recommends a value greater than 18 ...

Page 100: ... the VDD_MPU domain merged with the VDD_CORE domain C If a USB port is not used the respective VDDA1P8V_USB terminal may be connected to any 1 8 V power supply and the respective VDDA3P3V_USB terminal may be connected to any 3 3 V power supply If the system does not have a 3 3 V power supply the VDDA3P3V_USB terminal may be connected to ground D If the system uses mDDR or DDR2 memory devices VDDS_...

Page 101: ... inputs may be powered from the same source if the application only uses operating performance points OPPs that define a common power supply voltage for VDD_MPU and VDD_CORE The ZCE package option has the VDD_MPU domain merged with the VDD_CORE domain D If a USB port is not used the respective VDDA1P8V_USB terminal may be connected to any 1 8 V power supply and the respective VDDA3P3V_USB terminal...

Page 102: ...n has the VDD_MPU domain merged with the VDD_CORE domain C If a USB port is not used the respective VDDA1P8V_USB terminal may be connected to any 1 8 V power supply and the respective VDDA3P3V_USB terminal may be connected to any 3 3 V power supply If the system does not have a 3 3 V power supply the VDDA3P3V_USB terminal may be connected to ground D If the system uses mDDR or DDR2 memory devices ...

Page 103: ...ating performance points OPPs that define a common power supply voltage for VDD_MPU and VDD_CORE The ZCE package option has the VDD_MPU domain merged with the VDD_CORE domain D If a USB port is not used the respective VDDA1P8V_USB terminal may be connected to any 1 8 V power supply and the respective VDDA3P3V_USB terminal may be connected to any 3 3 V power supply If the system does not have a 3 3...

Page 104: ...power supplies E VDDS_RTC should be ramped at the same time or before CAP_VDD_RTC but these power inputs can be ramped independent of other power supplies if PMIC_POWER_EN functionality is not required If CAP_VDD_RTC is ramped after VDD_CORE there might be a small amount of additional leakage current on VDD_CORE The power sequence shown provides the lowest leakage option F To configure VDDSHVx 1 6...

Page 105: ...PRIL 2016 Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Power and Clocking Copyright 2011 2016 Texas Instruments Incorporated If none of the VDDSHVx 1 6 power supplies are configured as 3 3 V the VDDS power supply may ramp down along with the VDDSHVx 1 6 supplies or after all the VDDSHVx 1 6 supplies have ramped down It is recommended to mainta...

Page 106: ...nt DPLLs Core DPLL Per DPLL Display DPLL DDR DPLL MPU DPLL Figure 6 8 shows the power supply connectivity implemented in the AM335x device Table 6 1 provides the power supply requirements for the DPLL Figure 6 8 DPLL Power Supply Connectivity Table 6 1 DPLL Power Supply Requirements SUPPLY NAME DESCRIPTION MIN NOM MAX UNIT VDDA1P8V_USB0 Supply voltage range for USBPHY and PER DPLL Analog 1 8 V 1 7...

Page 107: ...rnal 32k RC oscillator CLK_RC32K or peripheral PLL CLK_32KHZ which receives a reference clock from the OSC0 input The OSC0 oscillator provides a 19 2 MHz 24 MHz 25 MHz or 26 MHz reference clock which is used to clock all non RTC functions and is connected to the XTALIN and XTALOUT terminals This clock source is referred to as the master oscillator CLK_M_OSC in the AM335x Sitara Processors Technica...

Page 108: ...e C0 specified by the crystal manufacturer plus any mutual capacitance Cpkg CPCB seen across the AM335x XTALIN and XTALOUT signals For recommended values of crystal circuit components see Table 6 2 Figure 6 9 OSC0 Crystal Circuit Schematic 1 Initial accuracy temperature drift and aging effects should be combined when evaluating a reference clock for this requirement Table 6 2 OSC0 Crystal Circuit ...

Page 109: ... 2011 2016 Texas Instruments Incorporated Table 6 3 OSC0 Crystal Circuit Characteristics NAME DESCRIPTION MIN TYP MAX UNIT Cpkg Shunt capacitance of package ZCE package 0 01 pF ZCZ package 0 01 pF Pxtal The actual values of the ESR ƒxtal and CL should be used to yield a typical crystal power dissipation value Using the maximum values specified for ESR ƒxtal and CL parameters yields a maximum power...

Page 110: ...ng to an invalid logic level which may increase leakage current through the oscillator input buffer Figure 6 11 OSC0 LVCMOS Circuit Schematic Table 6 4 OSC0 LVCMOS Reference Clock Requirements NAME DESCRIPTION MIN TYP MAX UNIT ƒ XTALIN Frequency LVCMOS reference clock 19 2 24 25 or 26 MHz Frequency LVCMOS reference clock stability and tolerance 1 50 50 ppm tdc XTALIN Duty cycle LVCMOS reference cl...

Page 111: ...l manufacturer The total load capacitance is CL C1 C2 C1 C2 Cshunt where Cshunt is the crystal shunt capacitance C0 specified by the crystal manufacturer plus any mutual capacitance Cpkg CPCB seen across the AM335x RTC_XTALIN and RTC_XTALOUT signals For recommended values of crystal circuit components see Table 6 5 Figure 6 12 OSC1 ZCE Package Crystal Circuit Schematic A Oscillator components Crys...

Page 112: ...l frequency stability and tolerance 1 Maximum RTC error 10 512 minutes per year 20 0 20 0 ppm Maximum RTC error 26 28 minutes per year 50 0 50 0 ppm CC1 C1 capacitance 12 0 24 0 pF CC2 C2 capacitance 12 0 24 0 pF Cshunt Shunt capacitance 1 5 pF ESR Crystal effective series resistance ƒxtal 32 768 kHz oscillator has nominal negative resistance of 725 kΩ and worst case negative resistance of 250 kΩ ...

Page 113: ...SS_RTC of the ZCZ package should be connected directly to the nearest PCB digital ground VSS In this mode of operation the RTC_XTALOUT terminal should not be used to source any external components The printed circuit board design should provide a mechanism to disconnect the RTC_XTALOUT terminal from any external components or signal traces that may couple noise into OSC1 via the RTC_XTALOUT termin...

Page 114: ...5 OSC1 Not Used Figure 6 17 shows the recommended oscillator connections when OSC1 of the ZCE package is not used and Figure 6 18 shows the recommended oscillator connections when OSC1 of the ZCZ package is not used An internal 10 kΩ pullup on the RTC_XTALIN terminal is turned on when OSC1 is disabled to prevent this input from floating to an invalid logic level which may increase leakage current ...

Page 115: ...g many configurations that yield different jitter performance There are also other unpredictable contributors to jitter performance such as application specific noise or crosstalk into the clock circuits Therefore there are no plans to specify jitter performance for these outputs 6 2 4 1 CLKOUT1 The CLKOUT1 signal can be output on the XDMA_EVENT_INTR0 terminal This terminal connects to one of seve...

Page 116: ...he Recommended Operating Conditions defined in Section 5 unless otherwise noted 7 1 1 Timing Parameters and Board Routing Analysis The timing parameter values specified in this data manual do not include delays by board routings As a good board design practice such delays must always be taken into account Timing values may be adjusted by increasing or decreasing such delays TI recommends using the...

Page 117: ...n of the AM335x Sitara Processors Technical Reference Manual SPRUH73 7 4 1 DCAN Electrical Data and Timing Table 7 1 Timing Requirements for DCANx Receive see Figure 7 1 NO MIN MAX UNIT ƒbaud baud Maximum programmable baud rate 1 Mbps 1 tw RX Pulse duration receive data bit H 2 1 H 2 1 ns 1 H Period of baud rate 1 programmed baud rate Table 7 2 Switching Characteristics for DCANx Transmit see Figu...

Page 118: ...Texas Instruments Incorporated 7 5 DMTimer 7 5 1 DMTimer Electrical Data and Timing 1 P Period of PICLKOCP interface clock Table 7 3 Timing Requirements for DMTimer 1 7 see Figure 7 2 NO MIN MAX UNIT 1 tc TCLKIN Cycle time TCLKIN 4P 1 1 ns 1 P Period of PICLKTIMER functional clock Table 7 4 Switching Characteristics for DMTimer 4 7 see Figure 7 2 NO PARAMETER MIN MAX UNIT 2 tw TIMERxH Pulse durati...

Page 119: ...gnals For example the AM335x terminal names for port 1 of the EMAC and switch have been changed from GMII to MII to indicate their Mode 0 function but the internal signal is named GMII However documents that describe the Ethernet switch reference these signals by their internal signal name For a cross reference of internal signal names to terminal names see Table 4 1 Operation of the EMAC and swit...

Page 120: ...ching Characteristics for MDIO_DATA see Figure 7 5 NO PARAMETER MIN TYP MAX UNIT 1 td MDC MDIO Delay time MDC high to MDIO valid 10 390 ns Figure 7 5 MDIO_DATA Timing Output Mode 7 6 1 2 EMAC and Switch MII Electrical Data and Timing Table 7 9 Timing Requirements for GMII x _RXCLK MII Mode see Figure 7 6 NO 10 Mbps 100 Mbps UNIT MIN TYP MAX MIN TYP MAX 1 tc RX_CLK Cycle time RX_CLK 399 96 400 04 3...

Page 121: ... 40 004 ns 2 tw TX_CLKH Pulse duration TX_CLK high 140 260 14 26 ns 3 tw TX_CLKL Pulse duration TX_CLK low 140 260 14 26 ns 4 tt TX_CLK Transition time TX_CLK 5 5 ns Figure 7 7 GMII x _TXCLK Timing MII Mode Table 7 11 Timing Requirements for GMII x _RXD 3 0 GMII x _RXDV and GMII x _RXER MII Mode see Figure 7 8 NO 10 Mbps 100 Mbps UNIT MIN TYP MAX MIN TYP MAX 1 tsu RXD RX_CLK Setup time RXD 3 0 val...

Page 122: ...356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated Table 7 12 Switching Characteristics for GMII x _TXD 3 0 and GMII x _TXEN MII Mode see Figure 7 9 NO PARAMETER 10 Mbps 100 Mbps UNIT MIN TYP MAX MIN TYP MAX 1 td TX_CLK TXD Delay time TX_CLK high to TXD 3 0 valid 5 25 5 25 ns td TX_CLK TX_EN Delay time TX_CLK to TX_EN valid Figure 7 9 GMI...

Page 123: ...UNIT 1 tc REF_CLK Cycle time REF_CLK 19 999 20 001 ns 2 tw REF_CLKH Pulse duration REF_CLK high 7 13 ns 3 tw REF_CLKL Pulse duration REF_CLK low 7 13 ns Figure 7 10 RMII x _REFCLK Timing RMII Mode Table 7 14 Timing Requirements for RMII x _RXD 1 0 RMII x _CRS_DV and RMII x _RXER RMII Mode see Figure 7 11 NO MIN TYP MAX UNIT 1 tsu RXD REF_CLK Setup time RXD 1 0 valid before REF_CLK 4 ns tsu CRS_DV ...

Page 124: ...mings Copyright 2011 2016 Texas Instruments Incorporated Table 7 15 Switching Characteristics for RMII x _TXD 1 0 and RMII x _TXEN RMII Mode see Figure 7 12 NO PARAMETER MIN TYP MAX UNIT 1 td REF_CLK TXD Delay time REF_CLK high to TXD 1 0 valid 2 13 ns td REF_CLK TXEN Delay time REF_CLK to TXEN valid 2 tr TXD Rise time TXD outputs 1 5 ns tr TX_EN Rise time TX_EN output 3 tf TXD Fall time TXD outpu...

Page 125: ...RCLK Timing RGMII Mode Table 7 17 Timing Requirements for RGMII x _RD 3 0 and RGMII x _RCTL RGMII Mode see Figure 7 14 NO 10 Mbps 100 Mbps 1000 Mbps UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX 1 tsu RD RXC Setup time RD 3 0 valid before RXC high or low 1 1 1 ns tsu RX_CTL RXC Setup time RX_CTL valid before RXC high or low 1 1 1 2 th RXC RD Hold time RD 3 0 valid after RXC high or low 1 1 1 ns th RXC ...

Page 126: ... Timing RGMII Mode Table 7 19 Switching Characteristics for RGMII x _TD 3 0 and RGMII x _TCTL RGMII Mode see Figure 7 16 NO PARAMETER 10 Mbps 100 Mbps 1000 Mbps UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX 1 tsk TD TXC TD to TXC output skew 0 5 0 5 0 5 0 5 0 5 0 5 ns tsk TX_CTL TXC TX_CTL to TXC output skew 0 5 0 5 0 5 0 5 0 5 0 5 2 tt TD Transition time TD 0 75 0 75 0 75 ns tt TX_CTL Transition time ...

Page 127: ...ble 7 21 and Table 7 22 assume testing over the recommended operating conditions and electrical characteristic conditions shown in Table 7 20 see Figure 7 17 through Figure 7 21 Table 7 20 GPMC and NOR Flash Timing Conditions Synchronous Mode PARAMETER MIN TYP MAX UNIT Input Conditions tR Input signal rise time 1 5 ns tF Input signal fall time 1 5 ns Output Condition CLOAD Output load capacitance ...

Page 128: ...ge to output lower byte enable and command latch enable gpmc_be0n_cle output upper byte enable gpmc_be1n invalid 11 D 4 2 3 D 4 1 9 D 4 3 3 D 4 6 9 ns F7 td clkL be x nIV Delay time gpmc_clk falling edge to gpmc_nbe0_cle gpmc_nbe1 invalid 12 D 4 2 3 D 4 1 9 D 4 3 3 D 4 6 9 ns F7 td clkL be x nIV Delay time gpmc_clk falling edge to gpmc_nbe0_cle gpmc_nbe1 invalid 13 D 4 2 3 D 4 1 9 D 4 3 3 D 4 11 9...

Page 129: ...ad E CSRdOffTime AccessTime TimeParaGranularity 1 GPMC_FCLK 17 For burst write E CSWrOffTime AccessTime TimeParaGranularity 1 GPMC_FCLK 17 6 For csn falling edge CS activated Case GpmcFCLKDivider 0 F 0 5 CSExtraDelay GPMC_FCLK 17 Case GpmcFCLKDivider 1 F 0 5 CSExtraDelay GPMC_FCLK 17 if ClkActivationTime and CSOnTime are odd or ClkActivationTime and CSOnTime are even F 1 0 5 CSExtraDelay GPMC_FCLK...

Page 130: ...ExtraDelay GPMC_FCLK 17 if OEOffTime ClkActivationTime 2 is a multiple of 3 9 For WE falling edge WE activated Case GpmcFCLKDivider 0 I 0 5 WEExtraDelay GPMC_FCLK 17 Case GpmcFCLKDivider 1 I 0 5 WEExtraDelay GPMC_FCLK 17 if ClkActivationTime and WEOnTime are odd or ClkActivationTime and WEOnTime are even I 1 0 5 WEExtraDelay GPMC_FCLK 17 otherwise Case GpmcFCLKDivider 2 I 0 5 WEExtraDelay GPMC_FCL...

Page 131: ...3356 AM3354 AM3352 AM3351 www ti com SPRS717J OCTOBER 2011 REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A In gpmc_csn x x is equal to 0 1 2 3 4 or 5 B In gpmc_wait x x is equal to 0 or 1 Figure 7 17 GPMC and NOR Flash Synchronous Single Rea...

Page 132: ... AM3356 AM3354 AM3352 AM3351 SPRS717J OCTOBER 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A In gpmc_csn x x is equal to 0 1 2 3 4 or 5 B In gpmc_wait x x is equal to 0 or 1 Figure 7 18 GPMC and NOR Flash Synchronous Burst R...

Page 133: ... AM3357 AM3356 AM3354 AM3352 AM3351 www ti com SPRS717J OCTOBER 2011 REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A In gpmc_csn x x is equal to 0 1 2 3 4 or 5 B In gpmc_wait x x is equal to 0 or 1 Figure 7 19 GPMC and NOR Flash Synchronous ...

Page 134: ... AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 SPRS717J OCTOBER 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A In gpmc_csn x x is equal to 0 1 2 3 4 or 5 B In gpmc_wait x x is equal to 0 or 1 Figure 7 20 GPMC and Multiplexed NOR...

Page 135: ...135 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 www ti com SPRS717J OCTOBER 2011 REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A In gpmc_csn x x is equal to 0 1 2 3 4 or 5 B In gpmc_wait x x is equal to 0 or 1 Figure 7 21 GPMC and Multi...

Page 136: ...Delay time input data gpmc_ad 15 0 capture from internal functional clock GPMC_FCLK 3 4 4 ns FI3 Delay time output chip select gpmc_csn x generation from internal functional clock GPMC_FCLK 3 6 5 6 5 ns FI4 Delay time output address gpmc_a 27 1 generation from internal functional clock GPMC_FCLK 3 6 5 6 5 ns FI5 Delay time output address gpmc_a 27 1 valid from internal functional clock GPMC_FCLK 3...

Page 137: ...l functional clock period in ns Table 7 26 GPMC and NOR Flash Switching Characteristics Asynchronous Mode NO PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX tR d Rise time output data gpmc_ad 15 0 2 2 ns tF d Fall time output data gpmc_ad 15 0 2 2 ns FA0 tw be x nV Pulse duration output lower byte enable and command latch enable gpmc_be0n_cle output upper byte enable gpmc_be1n valid time Read N 12 N 1...

Page 138: ...anularity 1 GPMC_FCLK 14 with n being the page burst access number 2 For reading B ADVRdOffTime CSOnTime TimeParaGranularity 1 0 5 ADVExtraDelay CSExtraDelay GPMC_FCLK 14 For writing B ADVWrOffTime CSOnTime TimeParaGranularity 1 0 5 ADVExtraDelay CSExtraDelay GPMC_FCLK 14 3 C OEOffTime CSOnTime TimeParaGranularity 1 0 5 OEExtraDelay CSExtraDelay GPMC_FCLK 14 4 D PageBurstAccessTime TimeParaGranula...

Page 139: ...rmation and Timings Copyright 2011 2016 Texas Instruments Incorporated A In gpmc_csn x x is equal to 0 1 2 3 4 or 5 In gpmc_wait x x is equal to 0 or 1 B FA5 parameter illustrates amount of time required to internally sample input data It is expressed in number of GPMC functional clock cycles From start of read cycle and after FA5 functional clock cycles input data will be internally sampled by ac...

Page 140: ...3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A In gpmc_csn x x is equal to 0 1 2 3 4 or 5 In gpmc_wait x x is equal to 0 or 1 B FA5 parameter illustrates amount of time required to internally sample input data It is expressed in number of GPMC functional clock cycles From start of read cycle and after FA5 functional clock cycles input dat...

Page 141: ...ssed in number of GPMC functional clock cycles From start of read cycle and after FA21 functional clock cycles first input page data will be internally sampled by active functional clock edge FA21 calculation must be stored inside AccessTime register bits field C FA20 parameter illustrates amount of time required to internally sample successive input page data It is expressed in number of GPMC fun...

Page 142: ...57 AM3356 AM3354 AM3352 AM3351 SPRS717J OCTOBER 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A In gpmc_csn x x is equal to 0 1 2 3 4 or 5 In gpmc_wait x x is equal to 0 or 1 Figure 7 25 GPMC and NOR Flash Asynchronous Write ...

Page 143: ...nformation and Timings Copyright 2011 2016 Texas Instruments Incorporated A In gpmc_csn x x is equal to 0 1 2 3 4 or 5 In gpmc_wait x x is equal to 0 or 1 B FA5 parameter illustrates amount of time required to internally sample input data It is expressed in number of GPMC functional clock cycles From start of read cycle and after FA5 functional clock cycles input data will be internally sampled by...

Page 144: ... AM3357 AM3356 AM3354 AM3352 AM3351 SPRS717J OCTOBER 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A In gpmc_csn x x is equal to 0 1 2 3 4 or 5 In gpmc_wait x x is equal to 0 or 1 Figure 7 27 GPMC and Multiplexed NOR Flash As...

Page 145: ...pmc_advn_ale generation from internal functional clock GPMC_FCLK 3 6 5 6 5 ns GNFI5 Delay time output lower byte enable and command latch enable gpmc_be0n_cle generation from internal functional clock GPMC_FCLK 3 6 5 6 5 ns GNFI6 Delay time output enable gpmc_oen generation from internal functional clock GPMC_FCLK 3 6 5 6 5 ns GNFI7 Delay time output write enable gpmc_wen generation from internal ...

Page 146: ... enable gpmc_advn_ale high to output write enable gpmc_wen valid C 3 0 2 C 3 2 0 C 3 5 C 3 5 ns GNF8 tw wenIV aleIV Delay time output write enable gpmc_wen invalid to output address valid and address latch enable gpmc_advn_ale invalid F 6 0 2 F 6 2 0 F 6 5 F 6 5 ns GNF9 tc wen Cycle time write H 8 H 8 ns GNF10 td csnV oenV Delay time output chip select gpmc_csn x 13 valid to output enable gpmc_oen...

Page 147: ...8 AM3357 AM3356 AM3354 AM3352 AM3351 www ti com SPRS717J OCTOBER 2011 REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated 1 In gpmc_csn x x is equal to 0 1 2 3 4 or 5 Figure 7 28 GPMC and NAND Flash Command Latch Cycle 1 In gpmc_csn x x is equal t...

Page 148: ...011 2016 Texas Instruments Incorporated 1 GNF12 parameter illustrates amount of time required to internally sample input data It is expressed in number of GPMC functional clock cycles From start of read cycle and after GNF12 functional clock cycles input data will be internally sampled by active functional clock edge GNF12 value must be stored inside AccessTime register bits field 2 GPMC_FCLK is a...

Page 149: ... 1 tc DDR_CK tc DDR_CKn Cycle time DDR_CK and DDR_CKn 5 1 ns 1 The JEDEC JESD209B specification only defines the maximum clock period for LPDDR333 and faster speed bin LPDDR memory devices To determine the maximum clock period see the respective LPDDR memory data sheet Figure 7 32 LPDDR Memory Interface Clock Timing 7 7 2 1 2 LPDDR Interface This section provides the timing specification for the L...

Page 150: ...NC A NC 150 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 SPRS717J OCTOBER 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A Enable internal weak pulldown on these pins For details see the EMIF section of the AM335x Sitara P...

Page 151: ...ted with a clock frequency less than 200 MHz lower speed grade LPDDR devices may be used if the minimum clock period specified for the LPDDR device is less than or equal to the minimum clock period selected for the AM335x LPDDR interface 7 7 2 1 2 3 PCB Stackup The minimum stackup required for routing the AM335x device is a four layer stackup as shown in Table 7 33 Additional layers may be added t...

Page 152: ...on 1 6 Number of layers between LPDDR routing layer and reference ground plane 0 7 PCB routing feature size 4 mils 8 PCB trace width w 4 mils 9 PCB BGA escape via pad size 2 18 20 mils 10 PCB BGA escape via hole size 2 10 mils 11 Single ended impedance Zo 3 50 75 Ω 12 Impedance control 4 5 Zo 5 Zo Zo 5 Ω 1 For the LPDDR device BGA pad size see the LPDDR device manufacturer documentation 2 A 20 10 ...

Page 153: ... the placement is to limit the maximum trace lengths and allow for proper routing space For single memory LPDDR systems the second LPDDR device is omitted from the placement Figure 7 34 AM335x Device and LPDDR Device Placement Table 7 35 Placement Specifications 1 NO PARAMETER MIN MAX UNIT 1 X 2 3 1750 mils 2 Y 2 3 1280 mils 3 Y Offset 2 3 4 650 mils 4 Clearance from non LPDDR signal to LPDDR keep...

Page 154: ... layer No breaks should be allowed in the reference ground or VDDS_DDR power plane in this region In addition the VDDS_DDR power plane should cover the entire keepout region Figure 7 35 LPDDR Keepout Region 7 7 2 1 2 6 Bulk Bypass Capacitors Bulk bypass capacitors are required for moderate speed bypassing of the LPDDR and other circuitry Table 7 36 contains the minimum numbers and capacitance requ...

Page 155: ...ection via 35 mils 7 Number of connection vias for each LPDDR device power and ground terminal 1 Vias 8 Trace length from LPDDR device power and ground terminal to connection via 35 mils 9 AM335x VDDS_DDR HS bypass capacitor count 3 10 Devices 10 AM335x VDDS_DDR HS bypass capacitor total capacitance 0 6 μF 11 LPDDR device HS bypass capacitor count 3 4 8 Devices 12 LPDDR device HS bypass capacitor ...

Page 156: ...ent of serial terminations for DQS x and DQ x net class signals should be determined based on PCB analysis Placement of serial terminations for ADDR_CTRL net class signals should be close to the AM335x device Table 7 40 shows the specifications for the serial terminators in such cases Table 7 40 LPDDR Signal Terminations NO PARAMETER MIN TYP MAX UNIT 1 CK net class 1 0 22 Zo 2 Ω 2 ADDR_CTRL net cl...

Page 157: ...2 3 25 mils 3 CK B to CK C skew length mismatch 25 mils 4 Center to center CK to other LPDDR trace spacing 4 4w 5 CK and ADDR_CTRL nominal trace length 5 CACLM 50 CACLM CACLM 50 mils 6 ADDR_CTRL to CK skew length mismatch 100 mils 7 ADDR_CTRL to ADDR_CTRL skew length mismatch 100 mils 8 Center to center ADDR_CTRL to other LPDDR trace spacing 4 4w 9 Center to center ADDR_CTRL to other ADDR_CTRL tra...

Page 158: ...DQS x to other LPDDR trace spacing 2 4w 3 DQS x and DQ x nominal trace length 3 DQLM 50 DQLM DQLM 50 mils 4 DQ x to DQS x skew length mismatch 3 100 mils 5 DQ x to DQ x skew length mismatch 3 100 mils 6 Center to center DQ x to other LPDDR trace spacing 2 4 4w 7 Center to center DQ x to other DQ x trace spacing 2 5 3w 1 DQS x represents the DQS0 and DQS1 clock net classes and DQ x represents the D...

Page 159: ...the DDR2 interface as a PCB design and manufacturing specification The design rules constrain PCB trace length PCB trace skew signal integrity cross talk and signal timing These rules when followed result in a reliable DDR2 memory system without the need for a complex timing closure process For more information regarding the guidelines for using this DDR2 specification see the Understanding TI s P...

Page 160: ...T T T T T T T T 160 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 SPRS717J OCTOBER 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A VDDS_DDR is the power supply for the DDR2 memories and the AM335x DDR2 interface B One of t...

Page 161: ...S CAS RAS WE CKE CK CK VREF ODT 0 1 µF B 161 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 www ti com SPRS717J OCTOBER 2011 REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A VDDS_DDR is the power supply for the DDR2 memories and the AM335x ...

Page 162: ...the DDR2 device is less than or equal to the minimum clock period selected for the AM335x DDR2 interface 2 Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backwards compatibility 3 92 terminal devices are also supported for legacy reasons New designs will migrate to 84 terminal DDR2 devices Electrically the 92 and 84 terminal DDR2 devices are the same 7 7 2 2 2 3 PCB Stackup The ...

Page 163: ...on 1 6 Number of layers between DDR2 routing layer and reference ground plane 0 7 PCB routing feature size 4 mils 8 PCB trace width w 4 mils 9 PCB BGA escape via pad size 2 18 20 mils 10 PCB BGA escape via hole size 2 10 mils 11 Single ended impedance Zo 3 50 75 Ω 12 Impedance control 4 5 Zo 5 Zo Zo 5 Ω 1 For the DDR2 device BGA pad size see the DDR2 device manufacturer documentation 2 A 20 10 via...

Page 164: ...of the placement is to limit the maximum trace lengths and allow for proper routing space For single memory DDR2 systems the second DDR2 device is omitted from the placement Figure 7 41 AM335x Device and DDR2 Device Placement Table 7 47 Placement Specifications 1 NO PARAMETER MIN MAX UNIT 1 X 2 3 1750 mils 2 Y 2 3 1280 mils 3 Y Offset 2 3 4 650 mils 4 Clearance from non DDR2 signal to DDR2 keepout...

Page 165: ...s should be allowed in the reference ground or VDDS_DDR power plane in this region In addition the VDDS_DDR power plane should cover the entire keepout region Figure 7 42 DDR2 Keepout Region 7 7 2 2 2 6 Bulk Bypass Capacitors Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry Table 7 48 contains the minimum numbers and capacitance required for the bulk...

Page 166: ...ber of connection vias for each DDR2 device power and ground terminal 1 vias 8 Trace length from DDR2 device power and ground terminal to connection via 35 mils 9 AM335x VDDS_DDR HS bypass capacitor count 3 10 devices 10 AM335x VDDS_DDR HS bypass capacitor total capacitance 0 6 μF 11 DDR2 device HS bypass capacitor count 3 4 8 devices 12 DDR2 device HS bypass capacitor total capacitance 4 0 4 μF 1...

Page 167: ... EMI issues 3 Series termination values should be uniform across net class 4 Zo is the DDR2 PCB trace characteristic impedance 5 No external termination resistors are allowed and ODT must be used for these net classes If the DDR2 interface is operated at a lower frequency 200 MHz clock rate on device terminations are not specifically required for the DQS x and DQ x net class signals and serial ter...

Page 168: ... Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated 7 7 2 2 2 10 DDR_VREF Routing DDR_VREF is used as a reference by the input buffers of the DDR2 memories as well as the AM335x device DDR_VREF is intended to be half the DDR2 power supply voltage and should be created usi...

Page 169: ...DR2 trace spacing 4 4w 5 CK and ADDR_CTRL nominal trace length 5 CACLM 50 CACLM CACLM 50 mils 6 ADDR_CTRL to CK skew length mismatch 100 mils 7 ADDR_CTRL to ADDR_CTRL skew length mismatch 100 mils 8 Center to center ADDR_CTRL to other DDR2 trace spacing 4 4w 9 Center to center ADDR_CTRL to other ADDR_CTRL trace spacing 4 3w 10 ADDR_CTRL A to B and ADDR_CTRL A to C skew length mismatch 2 100 mils 1...

Page 170: ...0 mils 6 DQ x to DQ x skew length mismatch 4 100 mils 7 Center to center DQ x to other DDR2 trace spacing 3 5 4w 8 Center to center DQ x to other DQ x trace spacing 3 6 3w 1 DQS x represents the DQS0 and DQS1 clock net classes and DQ x represents the DQ0 and DQ1 signal net classes 2 Differential impedance should be Zo x 2 where Zo is the single ended impedance defined in Table 7 46 3 Center to cen...

Page 171: ...n one device is placed on the top of the board and the second device is placed on the bottom of the board 1 The JEDEC JESD79 3F Standard defines the maximum clock period of 3 3 ns for all standard speed bin DDR3 and DDR3L memory devices Therefore all standard speed bin DDR3 and DDR3L memory devices are required to operate at 303 MHz Figure 7 46 DDR3 Memory Interface Clock Timing 7 7 2 3 1 1 DDR3 v...

Page 172: ...anding TI s PCB Routing Rule Based DDR Timing Specification application report SPRAAV0 This application report provides generic guidelines and approach All the specifications provided in the data manual take precedence over the generic guidelines and must be adhered to for a reliable DDR3 interface operation 7 7 2 3 3 1 DDR3 Interface Schematic The DDR3 interface schematic varies depending upon th...

Page 173: ...15 CAS RAS WE RESET CKE ZQ VREFDQ VREFCA ZQ Zo Zo Zo Zo DDR_VREF DDR_VTT VDDS_DDR Termination is required See terminator comments Zo Value determined according to the DDR3 memory device data sheet ZQ 0 1 µF 173 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 www ti com SPRS717J OCTOBER 2011 REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM...

Page 174: ...ZQ VREFDQ VREFCA ZQ Value determined according to the DDR3 memory device data sheet ZQ 1 K Ω 1 VDDS_DDR A 0 1 µF 0 1 µF 1 K Ω 1 DDR_VREF 174 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 SPRS717J OCTOBER 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Tex...

Page 175: ...A15 CAS RAS WE RESET CKE ZQ VREFDQ VREFCA Termination is required See terminator comments Zo Value determined according to the DDR3 memory device data sheet ZQ 0 1 µF ZQ Zo Zo Zo Zo DDR_VREF DDR_VTT VDDS_DDR TDQS NC NC TDQS 0 1 µF DM TDQS DDR_DQM1 DM TDQS DDR_DQM0 175 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 www ti com SPRS717J OCTOBER 2011 REVISED APRIL 2016 Submit Documentation Feedback ...

Page 176: ...vice count 1 1 2 devices 1 For valid DDR3 device configurations and device counts see Section 7 7 2 3 3 1 Figure 7 47 and Figure 7 49 7 7 2 3 3 3 PCB Stackup The minimum stackup for routing the DDR3 interface is a four layer stack up as shown in Table 7 59 Additional layers may be added to the PCB stackup to accommodate other circuitry enhance signal integrity and electromagnetic interference perf...

Page 177: ...he DDR3 device BGA pad size see the DDR3 device manufacturer documentation 2 Ground reference layers are preferred over power reference layers Be sure to include bypass caps to accommodate reference layer return current as the trace routes switch routing layers 3 No traces should cross reference plane cuts within the DDR3 routing region High speed signal traces crossing reference plane cuts create...

Page 178: ...e devices are mounted The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space Figure 7 50 Placement Specifications Table 7 61 Placement Specifications 1 NO PARAMETER MIN MAX UNIT 1 X1 2 3 4 1000 mils 2 X2 2 3 600 mils 3 Y Offset 2 3 4 1500 mils 4 Clearance from non DDR3 signal to DDR3 keepout region 5 6 4 w 1 DDR3 keepout region to encompass e...

Page 179: ...breaks should be allowed in the reference ground or VDDS_DDR power plane in this region In addition the VDDS_DDR power plane should cover the entire keepout region Figure 7 51 DDR3 Keepout Region 7 7 2 3 3 6 Bulk Bypass Capacitors Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry Table 7 62 contains the minimum numbers and capacitance required for the...

Page 180: ...apacitor count 6 12 devices 8 DDR3 device HS bypass capacitor total capacitance 6 0 85 μF 9 Number of connection vias for each HS bypass capacitor 7 8 2 vias 10 Trace length from bypass capacitor connect to connection via 2 8 35 100 mils 11 Number of connection vias for each DDR3 device power and ground terminal 9 1 vias 12 Trace length from DDR3 device power and ground terminal to connection via ...

Page 181: ...ol signals A typical DDR3 point to point topology may provide acceptable signal integrity without VTT termination System performance should be verified by performing signal integrity analysis using specific PCB design details before implementing this topology 7 7 2 3 3 10 DDR_VREF Routing DDR_VREF is used as a reference by the input buffers of the DDR3 memories as well as the AM335x device DDR_VRE...

Page 182: ...d 7 7 2 3 4 1 Two DDR3 Devices Two DDR3 devices are supported on the DDR3 interface consisting of two x8 DDR3 devices arranged as one 16 bit bank These two devices may be mounted on a single side of the PCB or may be mirrored in a pair to save board space at a cost of increased routing complexity and parts on the backside of the PCB 7 7 2 3 4 1 1 CK and ADDR_CTRL Topologies Two DDR3 Devices Figure...

Page 183: ... SPRS717J OCTOBER 2011 REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated Figure 7 54 CK Routing for Two Single Side DDR3 Devices Figure 7 55 ADDR_CTRL Routing for Two Single Side DDR3 Devices ...

Page 184: ...52 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated To save PCB space the two DDR3 memories may be mounted as a mirrored pair at a cost of increased routing and assembly complexity Figure 7 56 and Figure 7 57 show the routing for CK and ADDR_CTRL respectively for two DDR3 devices mirrored in a single pair configuration Figure 7 56 CK Routing for Two Mirr...

Page 185: ... Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated 7 7 2 3 4 2 One DDR3 Device A single DDR3 device is supported on the DDR3 interface consisting of one x16 DDR3 device arranged as one 16 bit bank 7 7 2 3 4 2 1 CK and ADDR_CTRL Topologies One DDR3 Device Figure 7 ...

Page 186: ...ng One DDR3 Device Figure 7 60 shows the CK routing for one DDR3 device Figure 7 61 shows the corresponding ADDR_CTRL routing Figure 7 60 CK Routing for One DDR3 Device Figure 7 61 ADDR_CTRL Routing for One DDR3 Device 7 7 2 3 5 Data Topologies and Routing Definition No matter the number of DDR3 devices used the data line topology is always point to point so its definition is simple 7 7 2 3 5 1 DQ...

Page 187: ...edback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated x 0 1 Figure 7 62 DQS x Topology x 0 1 Figure 7 63 DQ x Topology 7 7 2 3 5 2 DQS x and DQ x Routing Any Number of Allowed DDR3 Devices Figure 7 64 and Figure 7 65 show the DQS x and DQ x routing x 0 1 Figure 7 64 DQS x Routing With Any N...

Page 188: ...hattan distance can be determined given the placement Figure 7 66 shows this distance for two loads It is from this distance that the specifications on the lengths of the transmission lines for the address bus are determined CACLM is determined similarly for other address bus configurations that is it is based on the longest net of the CK and ADDR_CTRL net class For CK and ADDR_CTRL routing these ...

Page 189: ...ss only not CK net class Minimizing this skew is recommended but not required 8 CK net class only 9 CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes 300 mils For definition see Section 7 7 2 3 6 1 and Figure 7 66 10 Center to center spacing is allowed to fall to minimum w for up to 1250 mils of routed length 11 Signals from one DQ net class should be considered other DDR...

Page 190: ... DQ x trace spacing 8 10 3w 8 DQS x center to center spacing 11 9 DQS x center to center spacing to other net 8 4w 1 DQS x represents the DQS0 and DQS1 clock net classes and DQ x represents the DQ0 and DQ1 signal net classes 2 External termination disallowed Data termination should use built in ODT functionality 3 DQLMn is the longest Manhattan distance of a byte For definition see Section 7 7 2 3...

Page 191: ...6 µs 6 tsu SDAV SCLH Setup time SDA valid before SCL high 250 100 1 ns 7 th SCLL SDAV Hold time SDA valid after SCL low 0 2 3 45 3 0 2 0 9 3 µs 8 tw SDAH Pulse duration SDA high between STOP and START conditions 4 7 1 3 µs 9 tr SDA Rise time SDA 1000 300 ns 10 tr SCL Rise time SCL 1000 300 ns 11 tf SDA Fall time SDA 300 300 ns 12 tf SCL Fall time SCL 300 300 ns 13 tsu SCLH SDAH Setup time high bef...

Page 192: ...FAST MODE UNIT MIN MAX MIN MAX 15 tc SCL Cycle time SCL 10 2 5 µs 16 tsu SCLH SDAL Setup time SCL high before SDA low for a repeated START condition 4 7 0 6 µs 17 th SDAL SCLL Hold time SCL low after SDA low for a START and a repeated START condition 4 0 6 µs 18 tw SCLL Pulse duration SCL low 4 7 1 3 µs 19 tw SCLH Pulse duration SCL high 4 0 6 µs 20 tsu SDAV SCLH Setup time SDA valid before SCL hi...

Page 193: ...OPP50 UNIT MIN MAX MIN MAX 1 tc TCK Cycle time TCK 81 5 104 5 ns 1a tw TCKH Pulse duration TCK high 40 of tc 32 6 41 8 ns 1b tw TCKL Pulse duration TCK low 40 of tc 32 6 41 8 ns 3 tsu TDI TCKH Input setup time TDI valid to TCK high 3 3 ns tsu TMS TCKH Input setup time TMS valid to TCK high 3 3 ns 4 th TCKH TDI Input hold time TDI valid from TCK high 8 05 8 05 ns th TCKH TMS Input hold time TMS val...

Page 194: ...m frame rate is determined by the image size in combination with the pixel clock rate Table 7 73 LCD Controller Timing Conditions PARAMETER MIN TYP MAX UNIT Output Condition CLOAD Output load capacitance LIDD mode 5 60 pF Raster mode 3 30 7 10 1 LCD Interface Display Driver LIDD Mode Table 7 74 Timing Requirements for LCD LIDD Mode see Figure 7 72 through Figure 7 80 NO OPP100 UNIT MIN MAX 16 tsu ...

Page 195: ...ransition time LCD_HYSNC 1 10 ns 12 td LCD_MEMORY_CLK LCD_PCLK Delay time LCD_MEMORY_CLK high to LCD_PCLK 0 7 ns 13 tt LCD_PCLK Transition time LCD_PCLK 1 10 ns 14 td LCD_MEMORY_CLK LCD_DATAZ Delay time LCD_MEMORY_CLK high to LCD_DATA 15 0 high Z 0 7 ns 15 td LCD_MEMORY_CLK LCD_DATA Delay time LCD_MEMORY_CLK high to LCD_DATA 15 0 driven 0 7 ns 19 tt LCD_MEMORY_CLK Transition time LCD_MEMORY_CLK 1 ...

Page 196: ...s Copyright 2011 2016 Texas Instruments Incorporated A Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK The first LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals The second LCD_MEMORY_CLK waveform is shown as E1 because the LCD_MEMORY_CLK signal is used to implement the E1 function in Hitachi mo...

Page 197: ...Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK The first LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals The second LCD_MEMORY_CLK waveform is s...

Page 198: ...6 www ti com Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A Motorola mode can be configured to perform asynchronous operations or synchronous operations When configured in asynchronous mode LCD_MEMORY_CLK is not required so it performs the CS1 function When c...

Page 199: ...SED APRIL 2016 Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A Motorola mode can be configured to perform asynchronous operations or synchronous operations When configured in asynchronous mode LCD_MEMORY_CLK is not required so it performs the CS1 function When...

Page 200: ...oduct Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A Motorola mode can be configured to perform asynchronous operations or synchronous operations When configured in asynchronous mode LCD_MEMORY_CLK is not required so it performs the CS1 function When configured in synchronous mode LCD_MEMORY_CLK ...

Page 201: ...IL 2016 Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A Intel mode can be configured to perform asynchronous operations or synchronous operations When configured in asynchronous mode LCD_MEMORY_CLK is not required so it performs the CS1 function When configure...

Page 202: ...016 www ti com Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A Intel mode can be configured to perform asynchronous operations or synchronous operations When configured in asynchronous mode LCD_MEMORY_CLK is not required so it performs the CS1 function When co...

Page 203: ...Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A Intel mode can be configured to perform asynchronous operations or synchronous operations When configured in asynchronous mode LCD_MEMORY_CLK is not required so it performs the CS1 function When configured in synchronous mode LCD_MEMORY_CLK p...

Page 204: ...nsition time LCD_VSYNC 0 5 2 4 0 5 2 4 ns 10 td LCD_PCLK LCD_HSYNC Delay time LCD_PCLK to LCD_HSYNC 3 0 3 0 1 7 1 9 ns 11 tt LCD_HSYNC Transition time LCD_HSYNC 0 5 2 4 0 5 2 4 ns 12 tt LCD_PCLK Transition time LCD_PCLK 0 5 2 4 0 5 2 4 ns 13 tt LCD_DATA Transition time LCD_DATA 0 5 2 4 0 5 2 4 ns Frame to frame timing is derived through the following parameters in the LCD RASTER_TIMING_1 register ...

Page 205: ...2 1 3 1 1 L 1 2 L 1 205 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 www ti com SPRS717J OCTOBER 2011 REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated Figure 7 81 LCD Raster Mode Display Format ...

Page 206: ...LMSB PPLLSB 16 1 to 2048 HBP 1 to 256 Line 1 1 to 256 HFP 1 to 64 HSW PPLMSB PPLLSB 16 1 to 2048 Line 2 LCD_AC_BIAS_EN ACTVID 11 206 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 SPRS717J OCTOBER 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instr...

Page 207: ...BIAS_EN ACB 0 to 255 ACB 0 to 255 1 4 P 4 1 3 P 3 1 2 P 2 1 L P L 1 6 P 6 1 2 P 2 1 1 P 1 1 L P L 1 to 256 11 207 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 www ti com SPRS717J OCTOBER 2011 REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated...

Page 208: ... 3 4 5 PPLMSB PPLLSB 16 x 1 to 2048 7 9 11 208 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 SPRS717J OCTOBER 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A The dashed portion of LCD_PCLK is only shown as a reference of t...

Page 209: ...PPLLSB 16 x 1 to 2048 11 1 2 3 2 1 P 1 1 1 4 5 209 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 www ti com SPRS717J OCTOBER 2011 REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A The dashed portion of LCD_PCLK is only shown as a reference ...

Page 210: ...it section of the McASP can transmit data in either a time division multiplexed TDM synchronous serial format or in a digital audio interface DIT format where the bit stream is encoded for SPDIF AES 3 IEC 60958 CP 430 transmission The receive section of the McASP peripheral supports the TDM synchronous serial format The McASP module can support one transmit data format either a TDM format or DIT f...

Page 211: ...5R 2 5 3 ns 5 tsu AFSRX ACLKRX Setup time McASP x _AFSR and McASP x _AFSX input valid before McASP x _ACLKR and McASP x _ACLKX ACLKR and ACLKX int 11 5 15 5 ns ACLKR and ACLKX ext in 4 6 ACLKR and ACLKX ext out 4 6 6 th ACLKRX AFSRX Hold time McASP x _AFSR and McASP x _AFSX input valid after McASP x _ACLKR and McASP x _ACLKX ACLKR and ACLKX int 1 1 ns ACLKR and ACLKX ext in 0 4 0 4 ACLKR and ACLKX...

Page 212: ...KRP CLKXP 1 B 212 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 SPRS717J OCTOBER 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A For CLKRP CLKXP 0 the McASP transmitter is configured for rising edge to shift data out and t...

Page 213: ...LKR and ACLKX int 0 6 0 6 ns ACLKR and ACLKX ext in 2 13 5 2 18 Delay time McASP x _ACLKR and McASP x _ACLKX transmit edge to McASP x _AFSR and McASP x _AFSX output valid with Pad Loopback ACLKR and ACLKX ext out 2 13 5 2 18 14 td ACLKX AXR Delay time McASP x _ACLKX transmit edge to McASP x _AXR output valid ACLKX int 0 6 0 6 ns ACLKX ext in 2 13 5 2 18 Delay time McASP x _ACLKX transmit edge to M...

Page 214: ...x _ACLKR X CLKRP CLKXP 0 B 214 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 SPRS717J OCTOBER 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated A For CLKRP CLKXP 1 the McASP transmitter is configured for falling edge to shift ...

Page 215: ...tion SPI_CLK low 0 5P 3 12 1 0 5P 3 12 1 0 5P 3 12 1 0 5P 3 12 1 ns 3 tw SPICLKH Typical pulse duration SPI_CLK high 0 5P 3 12 1 0 5P 3 12 1 0 5P 3 12 1 0 5P 3 12 1 ns 4 tsu SIMO SPICLK Setup time SPI_D x SIMO valid before SPI_CLK active edge 2 3 12 92 12 92 ns 5 th SPICLK SIMO Hold time SPI_D x SIMO valid after SPI_CLK active edge 2 3 12 92 12 92 ns 8 tsu CS SPICLK Setup time SPI_CS valid before ...

Page 216: ...n 3 Bit 1 Bit 0 PHA 1 EPOL 1 POL 0 POL 1 8 3 2 1 2 3 1 4 5 4 5 5 4 9 1 9 216 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 SPRS717J OCTOBER 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated Figure 7 88 SPI Slave Mode Receive T...

Page 217: ... n 3 Bit 1 Bit 0 PHA 1 EPOL 1 POL 0 POL 1 8 3 6 6 2 1 2 3 1 6 6 9 6 9 3 217 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 www ti com SPRS717J OCTOBER 2011 REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated Figure 7 89 SPI Slave Mode Transmit T...

Page 218: ... MAX MIN MAX MIN MAX 1 tc SPICLK Cycle time SPI_CLK 20 8 20 8 41 6 41 6 ns 2 tw SPICLKL Typical pulse duration SPI_CLK low 0 5P 1 04 1 0 5P 1 04 1 0 5P 2 08 1 0 5P 2 08 1 0 5P 1 04 1 0 5P 1 04 1 0 5P 2 08 1 0 5P 2 08 1 ns 3 tw SPICLKH Typical pulse duration SPI_CLK high 0 5P 1 04 1 0 5P 1 04 1 0 5P 2 08 1 0 5P 2 08 1 0 5P 1 04 1 0 5P 1 04 1 0 5P 2 08 1 0 5P 2 08 1 ns tr SPICLK Rising time SPI_CLK ...

Page 219: ...J OCTOBER 2011 REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated 4 Case P 20 8 ns A TCS 1 TSPICLKREF TCS is a bit field of MCSPI_CH i CONF register Case P 20 8 ns A TCS 0 5 Fratio TSPICLKREF TCS is a bit field of MCSPI_CH i CONF register Note P ...

Page 220: ...t n 2 Bit n 3 Bit 1 Bit 0 PHA 1 EPOL 1 POL 0 POL 1 8 9 3 6 6 2 1 2 3 1 6 6 220 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 SPRS717J OCTOBER 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright 2011 2016 Texas Instruments Incorporated Figure 7 91 SPI Master Mode Transm...

Page 221: ... Input signal fall time 1 5 ns Output Condition Cload Output load capacitance 3 30 pF Table 7 87 Timing Requirements for MMC x _CMD and MMC x _DAT 7 0 see Figure 7 92 NO 1 8 V MODE 3 3 V MODE UNIT MIN TYP MAX MIN TYP MAX 1 tsu CMDV CLKH Setup time MMC_CMD valid before MMC_CLK rising clock edge 4 1 4 1 ns 2 th CLKH CMDV Hold time MMC_CMD valid after MMC_CLK rising clock edge Industrial extended tem...

Page 222: ...8 ns fid CLK Identification mode frequency MMC_CLK 400 400 kHz tcid CLK Identification mode period MMC_CLK 2500 2500 ns 6 tw CLKL Pulse duration MMC_CLK low 0 5 P tf CLK 1 0 5 P tf CLK 1 ns 7 tw CLKH Pulse duration MMC_CLK high 0 5 P tr CLK 1 0 5 P tr CLK 1 ns 8 tr CLK Rise time all signals 10 to 90 2 2 2 2 ns 9 tf CLK Fall time all signals 10 to 90 2 2 2 2 ns 1 P MMC_CLK period Figure 7 93 MMC x ...

Page 223: ...Information and Timings Copyright 2011 2016 Texas Instruments Incorporated Table 7 90 Switching Characteristics for MMC x _CMD and MMC x _DAT 7 0 High Speed Mode see Figure 7 95 NO PARAMETER OPP100 OPP50 UNIT MIN TYP MAX MIN TYP MAX 12 td CLKL CMD Delay time MMC_CLK rising clock edge to MMC_CMD transition 3 14 3 17 5 ns 13 td CLKL DAT Delay time MMC_CLK rising clock edge to MMC_DATx transition 3 1...

Page 224: ...ons PARAMETER MIN MAX UNIT Output Condition Cload Capacitive load for each bus line 30 pF 7 14 1 1 PRU ICSS PRU Direct Input Output Mode Electrical Data and Timing 1 P L3_CLK PRU ICSS ocp clock period 2 n 16 Table 7 92 PRU ICSS PRU Timing Requirements Direct Input Mode see Figure 7 96 NO MIN MAX UNIT 1 tw GPI Pulse width GPI 2 P 1 ns 2 tr GPI Rise time GPI 1 00 3 00 ns tf GPI Fall time GPI 1 00 3 ...

Page 225: ...lse duration CLOCKIN high 10 00 ns 4 tr CLOCKIN Rising time CLOCKIN 1 00 3 00 ns 5 tf CLOCKIN Falling time CLOCKIN 1 00 3 00 ns 6 tsu DATAIN CLOCKIN Setup time DATAIN valid before CLOCKIN 5 00 ns 7 th CLOCKIN DATAIN Hold time DATAIN valid after CLOCKIN 0 00 ns 8 tr DATAIN Rising time DATAIN 1 00 3 00 ns tf DATAIN Falling time DATAIN 1 00 3 00 ns Figure 7 98 PRU ICSS PRU Parallel Capture Timing Ris...

Page 226: ...td CLOCKOUT DATAOUT Delay time CLOCKOUT to DATAOUT valid 0 00 3 00 ns 6 tr DATAOUT Rising time DATAOUT 1 00 3 00 ns tf DATAOUT Falling time DATAOUT 1 00 3 00 ns Figure 7 101 PRU ICSS PRU Shift Out Timing 7 14 2 PRU ICSS EtherCAT PRU ICSS ECAT Table 7 97 PRU ICSS ECAT Timing Conditions PARAMETER MIN MAX UNIT Output Condition Cload Capacitive load for each bus line 30 pF 7 14 2 1 PRU ICSS ECAT Elect...

Page 227: ...A_IN Falling time EDIO_DATA_IN 1 00 3 00 ns Figure 7 102 PRU ICSS ECAT Input Validated with LATCH_IN Timing Table 7 99 PRU ICSS ECAT Timing Requirements Input Validated with SYNCx see Figure 7 103 NO MIN MAX UNIT 1 tw EDC_SYNCx_OUT Pulse width EDC_SYNCx_OUT 100 00 ns 2 tr EDC_SYNCx_OUT Rising time EDC_SYNCx_OUT 1 00 3 00 ns 3 tf EDC_SYNCx_OUT Falling time EDC_SYNCx_OUT 1 00 3 00 ns 4 tsu EDIO_DATA...

Page 228: ...ising time EDIO_SOF 1 00 3 00 ns 3 tf EDIO_SOF Falling time EDIO_SOF 1 00 3 00 ns 4 tsu EDIO_DATA_IN EDIO_SOF Setup time EDIO_DATA_IN valid before EDIO_SOF active edge 20 00 ns 5 th EDIO_SOF EDIO_DATA_IN Hold time EDIO_DATA_IN valid after EDIO_SOF active edge 20 00 ns 6 tr EDIO_DATA_IN Rising time EDIO_DATA_IN 1 00 3 00 ns tf EDIO_DATA_IN Falling time EDIO_DATA_IN 1 00 3 00 ns Figure 7 104 PRU ICS...

Page 229: ... 00 3 00 ns 6 tf EDIO_DATA_OUT Falling time EDIO_DATA_OUT 1 00 3 00 ns 7 tsk EDIO_DATA_OUT EDIO_DATA_OUT skew 8 00 ns 7 14 3 PRU ICSS MII_RT and Switch 1 Except when specified otherwise Table 7 103 PRU ICSS MII_RT Switch Timing Conditions PARAMETER MIN TYP MAX UNIT Input Conditions tR Input signal rise time 1 1 3 1 ns tF Input signal fall time 1 1 3 1 ns Output Condition CLOAD Output load capacita...

Page 230: ...CSS MDIO Switching Characteristics MDIO_DATA see Figure 7 108 NO MIN TYP MAX UNIT 1 td MDC MDIO Delay time MDC high to MDIO valid 10 390 ns Figure 7 108 PRU ICSS MDIO_DATA Timing Output Mode 7 14 3 2 PRU ICSS MII_RT Electrical Data and Timing Table 7 107 PRU ICSS MII_RT Timing Requirements MII_RXCLK see Figure 7 109 NO 10 Mbps 100 Mbps UNIT MIN TYP MAX MIN TYP MAX 1 tc RX_CLK Cycle time RX_CLK 399...

Page 231: ...40 004 ns 2 tw TX_CLKH Pulse duration TX_CLK high 140 260 14 26 ns 3 tw TX_CLKL Pulse duration TX_CLK low 140 260 14 26 ns 4 tt TX_CLK Transition time TX_CLK 3 3 ns Figure 7 110 PRU ICSS MII_TXCLK Timing Table 7 109 PRU ICSS MII_RT Timing Requirements MII_RXD 3 0 MII_RXDV and MII_RXER see Figure 7 111 NO 10 Mbps 100 Mbps UNIT MIN TYP MAX MIN TYP MAX 1 tsu RXD RX_CLK Setup time RXD 3 0 valid before...

Page 232: ...lay time TX_CLK high to TXD 3 0 valid 5 25 5 25 ns td TX_CLK TX_EN Delay time TX_CLK to TX_EN valid Figure 7 112 PRU ICSS MII_TXD 3 0 MII_TXEN Timing 7 14 4 PRU ICSS Universal Asynchronous Receiver Transmitter PRU ICSS UART 1 U UART baud time 1 programmed baud rate Table 7 111 Timing Requirements for PRU ICSS UART Receive see Figure 7 113 NO MIN MAX UNIT 3 tw RX Pulse duration receive start stop d...

Page 233: ... see the Universal Asynchronous Receiver Transmitter UART section of the AM335x Sitara Processors Technical Reference Manual SPRUH73 7 15 1 UART Electrical Data and Timing Table 7 113 Timing Requirements for UARTx Receive see Figure 7 114 NO MIN MAX UNIT 3 tw RX Pulse duration receive start stop data bit 0 96U 1 1 05U 1 ns 1 U UART baud time 1 programmed baud rate Table 7 114 Switching Characteris...

Page 234: ... MIR 0 576 Mbps and 1 152 Mbps Fast infrared FIR 4 Mbps Figure 7 115 illustrates the UART IrDA pulse parameters Table 7 115 and Table 7 116 list the signaling rates and pulse durations for UART IrDA receive and transmit modes Figure 7 115 UART IrDA Pulse Parameters Table 7 115 UART IrDA Signaling Rate and Pulse Duration Receive Mode SIGNALING RATE ELECTRICAL PULSE DURATION UNIT MIN MAX SIR 2 4 kbp...

Page 235: ...mings Copyright 2011 2016 Texas Instruments Incorporated Table 7 116 UART IrDA Signaling Rate and Pulse Duration Transmit Mode SIGNALING RATE ELECTRICAL PULSE DURATION UNIT MIN MAX SIR 2 4 kbps 78 1 78 1 µs 9 6 kbps 19 5 19 5 µs 19 2 kbps 9 75 9 75 µs 38 4 kbps 4 87 4 87 µs 57 6 kbps 3 25 3 25 µs 115 2 kbps 1 62 1 62 µs MIR 0 576 Mbps 414 419 ns 1 152 Mbps 206 211 ns FIR 4 Mbps single pulse 123 12...

Page 236: ...support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development support product X and P devices and TMDX development support tools are shipped against the following disclaimer Developmental product is intended for internal evaluation purposes Production devices and TMDS development support tools have been characterized fully and the qual...

Page 237: ...vides a stable and affordable platform to quickly start evaluation of Sitara ARM Cortex A8 AM335x Processors AM3351 AM3352 AM3354 AM3356 AM3358 and accelerate development for smart appliance industrial and networking applications It is a low cost development platform based on the ARM Cortex A8 processor that is integrated with options such as Dual Gigabit Ethernet DDR3 and LCD touch screen BeagleB...

Page 238: ... range of industrial automation equipment It enables low foot print designs in applications such as industrial automation factory automation or industrial communication with minimal external components and with best in class low power performance Acontis EtherCAT Master Stack Reference Design Highly portable software stack that can be used on various embedded platforms The EC Master supports the h...

Page 239: ... components including streaming protocols and internet radio services With this reference design TI offers a quick and easy transition path to the AM335x and WiLink8 platform solution This proven combo solution provides key advantages in this market category that helps bring your products to the next level Software Processor SDK for AM335X Sitara Processors Linux and TI RTOS support Unified softwa...

Page 240: ...ally selecting a mux configuration that satisfies the entered requirements Power Estimation Tool PET Provides users the ability to gain insight in to the power consumption of select TI processors The tool includes the ability for the user to choose multiple application scenarios and understand the power consumption as well as how advanced power saving techniques can be applied to further reduce ov...

Page 241: ...omization Modifying Board Library to Change UART Instance on AM335x Describes the procedure to modify the default UART0 example in the AM335x Processor SDK RTOS package to enable UART1 On the BeagleBone Black BBB P9 header pins 24 TX and 26 RX are connected to UART1 This procedure shows a test to verify that UART1 is enabled on the BBB High Speed Layout GuidelinesAs modern bus interface frequencie...

Page 242: ...features such as cross traffic hot plugging and different types of network configurations such as star ring and mixed topologies EtherNet IP on TI s Sitara AM335x Processors EtherNet IP EtherNet Industrial Protocol is an industrial automation networking protocol based on the IEEE 802 3 Ethernet standard that has dominated the world of IT networking for the past three decades PROFINET on TI s Sitar...

Page 243: ...lear Path to Open source Resources Ready to use open source hardware platform for rapid prototyping and firmware and software development Enable Security and Amp Up Chip Performance With Hardware Accelerated Cryptography Cryptography is one of several techniques or methodologies that are typically implemented in contemporary electronic systems to construct a secure perimeter around a device where ...

Page 244: ... At e2e ti com you can ask questions share knowledge explore ideas and help solve problems with fellow engineers TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices 8 6 Tradem...

Page 245: ... and substantially reduces PCB costs It allows PCB routing in only two signal layers four layers total due to the increased layer efficiency of the Via Channel BGA technology Via Channel technology implemented on the ZCE package makes it possible to build an AM335x based product with a 4 layer PCB but a 4 layer PCB may not meet system performance goals Therefore system performance using a 4 layer ...

Page 246: ...no Sb Br SNAGCU Level 3 260C 168 HR 0 to 90 AM3352BZCE30 AM3352BZCE30R ACTIVE NFBGA ZCE 298 1000 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR AM3352BZCE30 AM3352BZCE60 ACTIVE NFBGA ZCE 298 160 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 0 to 90 AM3352BZCE60 AM3352BZCEA30 ACTIVE NFBGA ZCE 298 160 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 40 to 105 AM3352BZCEA30 AM3352BZCEA30R ACTIVE NFBGA...

Page 247: ...52BZCZD60 ACTIVE NFBGA ZCZ 324 126 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 40 to 90 AM3352BZCZD60 AM3352BZCZD80 ACTIVE NFBGA ZCZ 324 126 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 40 to 90 AM3352BZCZD80 AM3352BZCZT60 ACTIVE NFBGA ZCZ 324 126 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 40 to 125 AM3352BZCZT60 AM3352BZCZT60R ACTIVE NFBGA ZCZ 324 1000 Green RoHS no Sb Br SNAGCU Level 3 ...

Page 248: ... ACTIVE NFBGA ZCZ 324 126 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 0 to 90 AM3356BZCZ30 AM3356BZCZ60 ACTIVE NFBGA ZCZ 324 126 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 0 to 90 AM3356BZCZ60 AM3356BZCZ80 ACTIVE NFBGA ZCZ 324 126 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 0 to 90 AM3356BZCZ80 AM3356BZCZA30 ACTIVE NFBGA ZCZ 324 126 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 40 to 10...

Page 249: ...r new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the producti...

Page 250: ...TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on ...

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Page 253: ...oduct s identified in such TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN including but not limited to any patent right copyright mask work right or other intellectual property right relating to any combination machine or p...

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