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Setup

2.1.13

J13 – VDD

This header is used to provide the V

DD

voltage (between 1.2 and 3.6 V) to the EVM if JP2 is not installed.

If JP2 is installed, the V

DD

voltage may be monitored at this header.

2.1.14

J14 – GND

This header is used to monitor the V

DD

voltage if JP2 is installed. If JP2 is not installed, this header is the

connection for the return connection of the applied V

DD

voltage.

2.1.15

J15 – INT Pin Output

This header provides the INT pin output on pin 1 with a convenient ground reference on pin 2.

2.1.16

J16 – V

IN

and GND Terminal Block

This terminal block is used instead of J1 or J3 when the input current exceeds 1 A. The leads to the input
supply should be twisted and kept as short as possible to minimize EMI transmission and reduce inductive
voltage droop during a load transient event. This voltage should be between 2.5 V and 5.5 V.

2.1.17

J17 – DCDC_A and GND Terminal Block

This terminal block is used, instead of J4 or J6, to connect to the load (processor) when the load current
exceeds 1 A. The leads to the load should be twisted and kept as short as possible to minimize EMI
transmission and reduce inductive voltage droop during a load transient event.

2.1.18

J18 – DCDC_B and GND Terminal Block

This terminal block is used, instead of J7 or J9, to connect to the load (processor) when the load current
exceeds 1 A. The leads to the load should be twisted and kept as short as possible to minimize EMI
transmission and reduce inductive voltage droop during a load transient event.

2.1.19

J19 – SYS I

2

C Connection from USB-TO-GPIO Adaptor

This connects the USB-TO-GPIO adaptor to the SYS I

2

C connection of the TPS650380. It provides the I

2

C

signals and a 3.3 V supply for powering V

DD

. This connector is keyed to prevent incorrect installation. Only

install a USB-TO-GPIO adaptor in either J19 or J25 at the same time.

2.1.20

J20 – SYS I

2

C Monitor Point and Alternate Connection

This header is provided to connect to or monitor the SYS I

2

C signals on the TPS650380EVM-054. If the

I

2

C signals are being sent via this header (and not via the USB-TO-GPIO adaptor), do not plug into the

J19 or J25 headers and provide a separate V

DD

supply between J13 and J14.

2.1.21

J21 – DVS I

2

C Monitor Point and Alternate Connection

This header is provided to connect to or monitor the DVS I

2

C signals on the TPS650380EVM-054. If the

I

2

C signals are being sent via this header (and not via the USB-TO-GPIO adaptor), do not plug into the

J19 or J25 headers and provide a separate V

DD

supply between J13 and J14.

2.1.22

J22 – DCDC_A Load Step Signal Input

This SMA connector accepts a signal input from a function generator that drives Q1 in order to evaluate
DCDC_A's transient response. This connector is not normally installed. TP3 can be used instead to apply
the signal.

2.1.23

J23 – DCDC_B Load Step Signal Input

This SMA connector accepts a signal input from a function generator that drives Q2 in order to evaluate
DCDC_B's transient response. This connector is not normally installed. TP4 can be used instead to apply
the signal.

5

SLVU720A – June 2012 – Revised November 2012

TPS650380EVM-054

Submit Documentation Feedback

Copyright © 2012, Texas Instruments Incorporated

Summary of Contents for PWR054-001

Page 1: ...DCDC_B vs Output Current VIN 3 6 V 12 5 Efficiency of DCDC_C vs Output Current VIN 3 6 V 12 6 Load Regulation VIN 3 6 V DCDC_A DCDC_B DCDC_C 0 96 V 13 7 Line Regulation DCDC_A DCDC_B DCDC_C 0 96 V IO...

Page 2: ...10 MB of free hard disk space 512 MB of RAM USB TO GPIO Adapter The USB TO GPIO adapter is the link that allows the PC and the EVM to communicate One end of the USB TO GPIO adapter connects to the PC...

Page 3: ...CDC_C disabled measured 14 mVPP across C6 Maximum efficiency DCDC_A VIN 3 6V DCDC_A 0 96V IOUT 200mA 90 1 2 Setup This section describes the jumpers and connectors on the EVM as well as how to properl...

Page 4: ...oltage As shipped the EVM is configured for local sensing of the output voltage If output voltage sensing at the load remote sensing is desired see the Remote Sense Resistors section This is a high im...

Page 5: ...ad transient event 2 1 19 J19 SYS I2 C Connection from USB TO GPIO Adaptor This connects the USB TO GPIO adaptor to the SYS I2 C connection of the TPS650380 It provides the I2 C signals and a 3 3 V su...

Page 6: ...alled in this case For normal operation without an external supply voltage the jumper should be installed 2 2 Software Setup The software is available at the TI website http focus ti com docs toolsw f...

Page 7: ...processor to either the output headers J4 and J6 J7 and J9 for currents below 1A and J10 and J12 or to the output terminal blocks J17 and J18 for currents greater than 1A The leads should be short and...

Page 8: ...he USB cable between the adapter and PC as instructed during the install process The host PC software also automatically searches on the Internet if connected for updates to the EVM software If a new...

Page 9: ...harge circuit on shutdown changing the mode status of each output voltage Forced PWM mode or Power Save Mode as well as an option to disable the nPG_x bit for each output voltage individually These se...

Page 10: ...acitors to be installed on each output voltage in order to reduce output ripple or lessen the voltage drop due to a load transient Some capacitors are located near the TPS650380 IC while others can be...

Page 11: ...s This section provides typical performance waveforms for the TPS650380EVM 054 The default register settings were used unless otherwise noted Figure 2 Efficiency vs Input Voltage DCDC_A DCDC_B DCDC_C...

Page 12: ...iciency 1 30 40 100 60 90 20 0 10 80 70 100 0 96V 1 2V 1 4V Test Results www ti com Figure 4 Efficiency of DCDC_B vs Output Current VIN 3 6 V Figure 5 Efficiency of DCDC_C vs Output Current VIN 3 6 V...

Page 13: ...Load Regulation 1 100 DCDC_A DCDC_B DCDC_C www ti com Test Results Figure 6 Load Regulation VIN 3 6 V DCDC_A DCDC_B DCDC_C 0 96 V Figure 7 Line Regulation DCDC_A DCDC_B DCDC_C 0 96 V IOUTA 3 4 A IOUT...

Page 14: ...ti com Figure 8 Start up VIN 3 6 V DCDC_A DCDC_B DCDC_C 0 96 V IOUTA IOUTB IOUTC 0 A Figure 9 Shutdown VIN 3 6 V DCDC_A DCDC_B DCDC_C 0 96 V IOUTA IOUTB IOUTC 0 A Active Output Capacitor Discharge En...

Page 15: ...gure 10 Shutdown VIN 3 6 V DCDC_A DCDC_B DCDC_C 0 96 V IOUTA IOUTB IOUTC 0 A Active Output Capacitor Discharge Enabled Figure 11 Output Voltage Ripple Measured Across C6 VIN 3 6 V DCDC_A 0 96 V DCDC_B...

Page 16: ...lts www ti com Figure 12 Input Voltage Ripple Measured Across C13 VIN 3 6 V DCDC_A 0 96 V DCDC_B DCDC_C Disabled IOUTA 5 A Figure 13 Load Transient Response VIN 3 6 V DCDC_A 0 96 V DCDC_B DCDC_C Disab...

Page 17: ...ww ti com Test Results Figure 14 Loop Response VIN 3 6 V DCDC_A 0 96 V DCDC_B DCDC_C Disabled IOUTA 5 A Figure 15 Thermal Performance VIN 3 6 V DCDC_A DCDC_B DCDC_C 0 96 V IOUTA 3 4 A IOUTB 1 85 A IOU...

Page 18: ...rt as possible to minimize trace inductance Careful attention has been given to the routing of high frequency current loops and a single point grounding scheme is used Also the majority of the heatsin...

Page 19: ...www ti com Board Layout Figure 17 Top Silk Layer 19 SLVU720A June 2012 Revised November 2012 TPS650380EVM 054 Submit Documentation Feedback Copyright 2012 Texas Instruments Incorporated...

Page 20: ...Board Layout www ti com Figure 18 Top Layer 20 TPS650380EVM 054 SLVU720A June 2012 Revised November 2012 Submit Documentation Feedback Copyright 2012 Texas Instruments Incorporated...

Page 21: ...www ti com Board Layout Figure 19 Layer 2 21 SLVU720A June 2012 Revised November 2012 TPS650380EVM 054 Submit Documentation Feedback Copyright 2012 Texas Instruments Incorporated...

Page 22: ...Board Layout www ti com Figure 20 Layer 3 22 TPS650380EVM 054 SLVU720A June 2012 Revised November 2012 Submit Documentation Feedback Copyright 2012 Texas Instruments Incorporated...

Page 23: ...www ti com Board Layout Figure 21 Bottom Layer 23 SLVU720A June 2012 Revised November 2012 TPS650380EVM 054 Submit Documentation Feedback Copyright 2012 Texas Instruments Incorporated...

Page 24: ...tself These devices are still fully tested TPS650380 devices Table 4 TPS650380EVM 054 Evaluation Components Count RefDes Value Description Size Part Number MFR 001 0 C1 C2 C25 Open Capacitor Ceramic X...

Page 25: ...L1 0 47uH 1 2 L2 0 47uH 1 2 L3 0 47uH 1 2 L4 0 47uH 1 2 L5 0 47uH 1 2 L6 0 47uH TP5 TP6 TP7 TP8 TP9 TP10 C5 100uF C17 C18 C19 C1 R22 10 0K 1 2 3 4 5 6 7 8 9 10 J25 R9 0 A1 PGND A2 LX_B2 A3 VIN_B A4 LX...

Page 26: ...4 7uF C27 10uF C2 R15 10 0K R17 100 R18 0 1 Q3 IRLR3715 TP14 TP15 TP13 R19 R20 R21 DCDC_A DCDC_B DCDC_C Schematic and Bill of Materials www ti com Figure 23 Schematic Page 2 6 2 Related Documentation...

Page 27: ...ncy energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC or ICES 003 rules which are designed to provide reasonable protection against radio fr...

Page 28: ...na type and its gain should be so chosen that the equivalent isotropically radiated power e i r p is not more than that necessary for successful communication This radio transmitter has been approved...

Page 29: ...roduct only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this product or 3 Use of this product only after you obtained the Technical Regulatio...

Page 30: ...property damage personal injury or death If there are questions concerning these ratings please contact a TI field representative prior to connecting interface electronics including input power and in...

Page 31: ...egulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided...

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