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Software Setup and Operation

It is recommended that the user press the 'READ' button at the top of the screen immediately after loading
the software to confirm that the software and cable connections are working properly. The message box at
the top right of the main panel (I

2

C Activity) displays all I

2

C activity. The message box at the bottom (USB

Bridge Connected) displays whether or not the USB-TO-GPIO connection is functional.

The software itself performs no calculations or computations and simply reads and writes to and from the
IC's registers through the I

2

C interface. Each register's bits can either be changed manually by changing

the boxes corresponding to each bit in the panel's top right half, or they can be changed through the drop-
down boxes and buttons in the rest of the panel. Some bits are reserved and not writeable. These will not
allow you to click on them to change their setting. For example, the CHIP_ID register (0x0Ah) is read only
and the TPS650380's main panel does not allow writes to those bits. The I

2

C bus speed is fixed at 100

kbps and this is noted at the bottom of the screen.

Following any change to an individual bit, drop-down box, or button, the user must write the new values to
the registers by either clicking the 'W' button to the left of each affected register or by clicking the 'WRITE'
button at the top of the screen.

In order to reduce the amount of manual reading and writing required, the two drop-downs at the top left of
the screen have been provided to do this automatically. The 'Auto Read' drop down allows the option of
automatically reading all the registers at specific time intervals. The 'Write On Changes' drop-down allows
the option of automatically writing a change to the registers as soon as it is made in the software.

The TPS650380 data sheet is available via the 'Help' menu (Internet access is required). The data sheet
discusses the functionality of the various register bits, which is also briefly repeated here.

The left side of the software main panel is divided into three parts--one for each output voltage. In each of
these sections, the output voltage, ramp rate, and sequencing timer time can be changed. In addition,
there are settings for enabling each output, enabling each output voltage's active output capacitor
discharge circuit on shutdown, changing the mode status of each output voltage (Forced PWM mode or
Power Save Mode), as well as an option to disable the nPG_x bit for each output voltage individually.
These settings correspond to all of registers 0x00h through 0x04h and 0x07h through 0x09h, as well as
portions of registers 0x05h and 0x06h.

In the bottom left corner of the software main panel are various common controls, including enabling the
over-current protection, forcing PWM mode on a ramp down of the output voltage, and resetting bits in the
exceptions register that correspond to various faults. These functions correspond to the remaining bits in
registers 0x05h and 0x06h.

The bottom right corner of the software main panel contains a status output screen. Displayed are the
status of the TPS650380's INT pin (high or low), the status of the exceptions register (0x06h), and the
contents of the CHIP_ID register (0x0Ah) which identifies the IC installed.

Finally, in the upper left corner of the software's main panel is a RESET button which writes a 1 to the
RESET bit of register 0x0Bh.

Circuit Use and Modifications

Besides the required circuitry to operate the TPS650380 (outlined in a white silk screen border on the
PCB), there are additional circuits present on the TPS650380EVM-054 that assist in evaluating the
TPS650380 as a processor power supply solution. Additionally, there are modifications that can be made
to adapt the circuit's performance to the needs of a particular application.

3.1

Load Step Circuit

The TPS650380EVM-054 contains a simple circuit that produces fast load current steps at the output of
the TPS650380. This evaluates the response of the TPS650380 to various load transients that might
occur in the system. An identical circuit is included for each output voltage. To operate the circuit on the
output of DCDC_A, connect a function generator to TP3. The output of the function generator should be a
square wave with a small duty cycle. The output high level controls the gate to source voltage of the
power transistor, Q1, and should be adjusted to generate the desired step current high level. The output
low level sets the step current low level. Good settings to start with are a square wave signal running at
100 Hz and 5% duty cycle going from 0V to 3V. These settings can be adjusted in order to generate the
desired load step.

9

SLVU720A – June 2012 – Revised November 2012

TPS650380EVM-054

Submit Documentation Feedback

Copyright © 2012, Texas Instruments Incorporated

Summary of Contents for PWR054-001

Page 1: ...DCDC_B vs Output Current VIN 3 6 V 12 5 Efficiency of DCDC_C vs Output Current VIN 3 6 V 12 6 Load Regulation VIN 3 6 V DCDC_A DCDC_B DCDC_C 0 96 V 13 7 Line Regulation DCDC_A DCDC_B DCDC_C 0 96 V IO...

Page 2: ...10 MB of free hard disk space 512 MB of RAM USB TO GPIO Adapter The USB TO GPIO adapter is the link that allows the PC and the EVM to communicate One end of the USB TO GPIO adapter connects to the PC...

Page 3: ...CDC_C disabled measured 14 mVPP across C6 Maximum efficiency DCDC_A VIN 3 6V DCDC_A 0 96V IOUT 200mA 90 1 2 Setup This section describes the jumpers and connectors on the EVM as well as how to properl...

Page 4: ...oltage As shipped the EVM is configured for local sensing of the output voltage If output voltage sensing at the load remote sensing is desired see the Remote Sense Resistors section This is a high im...

Page 5: ...ad transient event 2 1 19 J19 SYS I2 C Connection from USB TO GPIO Adaptor This connects the USB TO GPIO adaptor to the SYS I2 C connection of the TPS650380 It provides the I2 C signals and a 3 3 V su...

Page 6: ...alled in this case For normal operation without an external supply voltage the jumper should be installed 2 2 Software Setup The software is available at the TI website http focus ti com docs toolsw f...

Page 7: ...processor to either the output headers J4 and J6 J7 and J9 for currents below 1A and J10 and J12 or to the output terminal blocks J17 and J18 for currents greater than 1A The leads should be short and...

Page 8: ...he USB cable between the adapter and PC as instructed during the install process The host PC software also automatically searches on the Internet if connected for updates to the EVM software If a new...

Page 9: ...harge circuit on shutdown changing the mode status of each output voltage Forced PWM mode or Power Save Mode as well as an option to disable the nPG_x bit for each output voltage individually These se...

Page 10: ...acitors to be installed on each output voltage in order to reduce output ripple or lessen the voltage drop due to a load transient Some capacitors are located near the TPS650380 IC while others can be...

Page 11: ...s This section provides typical performance waveforms for the TPS650380EVM 054 The default register settings were used unless otherwise noted Figure 2 Efficiency vs Input Voltage DCDC_A DCDC_B DCDC_C...

Page 12: ...iciency 1 30 40 100 60 90 20 0 10 80 70 100 0 96V 1 2V 1 4V Test Results www ti com Figure 4 Efficiency of DCDC_B vs Output Current VIN 3 6 V Figure 5 Efficiency of DCDC_C vs Output Current VIN 3 6 V...

Page 13: ...Load Regulation 1 100 DCDC_A DCDC_B DCDC_C www ti com Test Results Figure 6 Load Regulation VIN 3 6 V DCDC_A DCDC_B DCDC_C 0 96 V Figure 7 Line Regulation DCDC_A DCDC_B DCDC_C 0 96 V IOUTA 3 4 A IOUT...

Page 14: ...ti com Figure 8 Start up VIN 3 6 V DCDC_A DCDC_B DCDC_C 0 96 V IOUTA IOUTB IOUTC 0 A Figure 9 Shutdown VIN 3 6 V DCDC_A DCDC_B DCDC_C 0 96 V IOUTA IOUTB IOUTC 0 A Active Output Capacitor Discharge En...

Page 15: ...gure 10 Shutdown VIN 3 6 V DCDC_A DCDC_B DCDC_C 0 96 V IOUTA IOUTB IOUTC 0 A Active Output Capacitor Discharge Enabled Figure 11 Output Voltage Ripple Measured Across C6 VIN 3 6 V DCDC_A 0 96 V DCDC_B...

Page 16: ...lts www ti com Figure 12 Input Voltage Ripple Measured Across C13 VIN 3 6 V DCDC_A 0 96 V DCDC_B DCDC_C Disabled IOUTA 5 A Figure 13 Load Transient Response VIN 3 6 V DCDC_A 0 96 V DCDC_B DCDC_C Disab...

Page 17: ...ww ti com Test Results Figure 14 Loop Response VIN 3 6 V DCDC_A 0 96 V DCDC_B DCDC_C Disabled IOUTA 5 A Figure 15 Thermal Performance VIN 3 6 V DCDC_A DCDC_B DCDC_C 0 96 V IOUTA 3 4 A IOUTB 1 85 A IOU...

Page 18: ...rt as possible to minimize trace inductance Careful attention has been given to the routing of high frequency current loops and a single point grounding scheme is used Also the majority of the heatsin...

Page 19: ...www ti com Board Layout Figure 17 Top Silk Layer 19 SLVU720A June 2012 Revised November 2012 TPS650380EVM 054 Submit Documentation Feedback Copyright 2012 Texas Instruments Incorporated...

Page 20: ...Board Layout www ti com Figure 18 Top Layer 20 TPS650380EVM 054 SLVU720A June 2012 Revised November 2012 Submit Documentation Feedback Copyright 2012 Texas Instruments Incorporated...

Page 21: ...www ti com Board Layout Figure 19 Layer 2 21 SLVU720A June 2012 Revised November 2012 TPS650380EVM 054 Submit Documentation Feedback Copyright 2012 Texas Instruments Incorporated...

Page 22: ...Board Layout www ti com Figure 20 Layer 3 22 TPS650380EVM 054 SLVU720A June 2012 Revised November 2012 Submit Documentation Feedback Copyright 2012 Texas Instruments Incorporated...

Page 23: ...www ti com Board Layout Figure 21 Bottom Layer 23 SLVU720A June 2012 Revised November 2012 TPS650380EVM 054 Submit Documentation Feedback Copyright 2012 Texas Instruments Incorporated...

Page 24: ...tself These devices are still fully tested TPS650380 devices Table 4 TPS650380EVM 054 Evaluation Components Count RefDes Value Description Size Part Number MFR 001 0 C1 C2 C25 Open Capacitor Ceramic X...

Page 25: ...L1 0 47uH 1 2 L2 0 47uH 1 2 L3 0 47uH 1 2 L4 0 47uH 1 2 L5 0 47uH 1 2 L6 0 47uH TP5 TP6 TP7 TP8 TP9 TP10 C5 100uF C17 C18 C19 C1 R22 10 0K 1 2 3 4 5 6 7 8 9 10 J25 R9 0 A1 PGND A2 LX_B2 A3 VIN_B A4 LX...

Page 26: ...4 7uF C27 10uF C2 R15 10 0K R17 100 R18 0 1 Q3 IRLR3715 TP14 TP15 TP13 R19 R20 R21 DCDC_A DCDC_B DCDC_C Schematic and Bill of Materials www ti com Figure 23 Schematic Page 2 6 2 Related Documentation...

Page 27: ...ncy energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC or ICES 003 rules which are designed to provide reasonable protection against radio fr...

Page 28: ...na type and its gain should be so chosen that the equivalent isotropically radiated power e i r p is not more than that necessary for successful communication This radio transmitter has been approved...

Page 29: ...roduct only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this product or 3 Use of this product only after you obtained the Technical Regulatio...

Page 30: ...property damage personal injury or death If there are questions concerning these ratings please contact a TI field representative prior to connecting interface electronics including input power and in...

Page 31: ...egulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided...

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