Texas Instruments PGA5807A, User Manual, Page: 16 / 75

Hardware and EVM Setup for Testing PGA5807A
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8. Supply an analog signal to the analog input SMA J10 , CH5(PGA_CH1) , of the PGA5807A EVM (that
is, –15 dBm, 5 MHz)
9. Supply an analog signal to the analog input signal to SMA J36 labeled PGA_CH5 , ADC_CH1 (+15
dbm, 5 MHz). ( Note, items 8 and 9 are not required simultaneously and not required at all for the initial
testing of a RAMP test pattern. As such, a single signal generator can be shared to supply both input
signals
)
3.2 PGA5807A EVM Header Configuration
The PGA5807A EVM is flexible in its configurability through the use of 3 pin headers. The default
configuration of the EVM is set to facilitate initial testing requiring minimal bench equipment by providing
an 80-MHz ADC sampling clock from an on-board crystal oscillator (XTAL).
Table 1 describes the purpose
of the 3-pin headers on the EVM while Figure 20 shows the default position. With this configuration, the
on-board XTAL is powered and providing an 80-MHz signal to a transformer which, in turn, provides a
differential sampling clock to the DUT.
Table 1. PGA5807A EVM Header Configuration
Jumper Default PIN 1 PIN 3 Circuit Description
Configuration Silkscreen Silkscreen
JP5 short pins 1.8V_AVDD n/a Power supply 1.8-V analog power supply for ADS5296A
JP6 short pins 1.8V_LVDD n/a Power supply 1.8-V digital power supply for ADS5296A
JP7 short pins 3.3V_AVDD n/a Power supply 3.3-V power supply for PGA5807A
JP9 short pins 1-2 XTAL CLK_IN Sampling clock Selects ADC sampling clock source: (1) XTAL OSC.
or (3) external source input to SMA J5 CLK_IN
JP11 short pins 1-2 CDC_3.3V GND Sampling clock Selects Power supply for CDC chip and on-board
XTAL oscillator: (1) GND or (3) +3.3V
JP12 short pins 1-2 XTAL XTAL_CDC Sampling clock Selects path for XTAL osc. signal: (1) to transformer
or (3) to CDC input
JP13 short pins 1-2 XTAL CLK_CDC Sampling clock Selects input source to CDC input: (1) XTAL osc. or
(3) external source input to SMA J5 CLK_IN
JP8 short pins 2-3 SE DIFF Sampling clock Selects ADC sampling clock configuration: (1) Single-
ended (3) Differential (must match JP8)
JP10 short pins 2-3 SE DIFF Sampling Clock Selects ADC sampling clock configuration: (1) Single-
ended or (3) Differential (must match JP10)
JP1 short pins 2-3 EVEN ODD INTERLEAVE_MUX Selects analog input channels to be interleaved: (1)
EVEN channels or (3) ODD channels
JP2 short pins 2-3 FTDI EVM INTERLEAVE_MUX Selects source of EVEN/ODD select: (1) GUI control
or (3) INTERLEAVE_MUX pin control
JP4 short pins 1-2 1.8V_AVDD GND SYNC ADS5296A SYNC Pin
JP14 short pins 2-3 5V GND EXT_REF AMP Selects power supply for EXT_REF AMP: (1) +5V or
(3) GND
JP15 Open 3.3V_AVDD GND PGA5807A RESET Pin PGA5807A RESET Pin On-board Control:
(1)PGA5807A is controlled by device pin;
(3)PGA5807A is controlled by SPI;
OPEN->RESET Pin is controlled by GUI"
JP550 short pins 1-2 ADCRESETZ n/a SPI Selects ADS5296A SPI control: (1) GUI control
JP52 short pins 1-2 PD n/a SPI Selects ADS5296A SPI control: (1) GUI control
JP48 short pins 1-2 SDOUT n/a SPI Selects ADS5296A SPI control: (1) GUI control
JP46 short pins 1-2 CSZ n/a SPI Selects ADS5296A SPI control: (1) GUI control
JP42 short pins 1-2 SCLK n/a SPI Selects ADS5296A SPI control: (1) GUI control
JP44 short pins 1-2 SDATA n/a SPI Selects ADS5296A SPI control: (1) GUI control
JP54 short pins 1-2 INTERLEAVE_M n/a SPI Selects ADS5296A SPI control: (1) GUI control
UX
16 PGA5807A, 8-Channel, High-Bandwidth, Analog Front-End Evaluation SLAU538 – October 2013
Module
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