Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Functional Description
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The VIDEOSYSC_CLKCTL register is used to stop or restart the module clocks. A write of 1 requests the
module logic to go idle and to stop the clock. A write of 0 requests a restart of logic and clock. When a
new request or command occurs, a module automatically exits the IDLE state and the clock starts. Clock
gating can be controlled for the following modules:
•
SL2 memory interface (controlled by the VIDEOSYSC_CLKCTL [5] SL2IFCLKEN bit)
• Sequencer memory and slave port (controlled by the VIDEOSYSC_CLKCTL [4] SEQMEMCLKEN bit)
• iVLCD module (controlled by the VIDEOSYSC_CLKCTL [2] IVLCDCLKEN bit)
• iME module (controlled by the VIDEOSYSC_CLKCTL [1] IMECLKEN bit)
• iLF module (controlled by the VIDEOSYSC_CLKCTL [0] ILFCLKEN bit)
For details, see Section 5.5.11 Video System Controller Registers.
The VIDEOSYSC_CLKDIV [1:0] SEQCLKDIV bit field is used to set a clock divider for the sequencer. A
divider of 1, 2, 3, or 4 is available. For details, see Section 5.5.11 , Video System Controller Registers.
5.3.7.5.3 Interrupt Handler
The video accelerator/sequencer SYSC has a single interrupt output, VIDEO_INT, which is an active
low-level interrupt connected to the DSP megamodule. Once asserted, it can be cleared explicitly only by
software. It can be enabled or disabled by software. It is asserted when one of the enabled event lines
gets asserted.
Table 5-7 lists these interrupts.
Table 5-7. LSYS Input Interrupts
Nb Name Description
7 Reserved Reserved
6 SEQ_MBX Sequencer mailbox IRQ
5 DMA_ERROR DMA error IRQ
4 HOST_ERROR HOST error IRQ
3 Reserved Reserved
2 IVLCD iVLCD IRQ
1 iLF iLF IRQ
0 iME iME IRQ
Four registers are defined for IRQ operation:
•
The IVA. VIDEOSYSC_IRQSTATE register tracks input events. Each event is associated with a bit in
this register. When the bit is set after an active pulse on the associated event line, this bit is kept active
(sticky) until the user explicitly writes 1 to that bit.
• The IVA. VIDEOSYSC_IRQMASK register controls the sensitivity of the interrupt line to input events.
Each event is associated with a bit in this register. When the user writes 1 to a bit, the associated
active event is not allowed to trigger an interrupt. When the user writes 0, the associated active event
triggers an interrupt.
• The IVA. VIDEOSYSC_IRQSET register is used to set the interrupt bits (used to test interrupt). Each
event is associated with a bit in this register. When the user writes 1 to a bit, the associated event is
set in the IVA.
VIDEOSYSC_IRQSTATE register. When the user writes 0, there is no effect.
• The IVA. VIDEOSYSC_IRQCLR register is used to clear the interrupt bits in the
IVA. VIDEOSYSC_IRQSTATE register. Each event is associated with a bit in this register. When the
user writes 1 to a bit, the associated event is cleared in the IVA. VIDEOSYSC_IRQSTATE register.
When the user writes 0, there is no effect.
5.3.8 Local Memories
The IVA2.2 subsystem integrates three memory controllers under the control of the DSP megamodule:
• DMC
• PMC
• UMC
740 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
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