Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Register Manual
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Table 5-702. VIDEOSYSC_IRQSTATE
Address Offset 0x0000 004C
Physical Address 0x0009 C04C Instance VIDEOSYSC
Description This register holds the interrupt status bits
Type w/1toSet
Bits Field Name Description Type Reset
31:8 RESERVED Reserved (not implemented) w/1toSet 0x000000
7 SPARE_1 Spare interrupt (reserved for future use) w/1toSet 0x0
6 SEQ_MBX SEQ Mailbox IRQ status w/1toSet 0x0
5 DMA_ERROR DMA error IRQ status w/1toSet 0x0
4 HOST_ERROR HOST error IRQ status w/1toSet 0x0
3 SPARE_0 Spare interrupt (reserved for future use) w/1toSet 0x0
2 IVLCD iVLCD IRQ status w/1toSet 0x0
1 iLF iLF IRQ status w/1toSet 0x0
0 iME iME IRQ status w/1toSet 0x0
Table 5-703. Register Call Summary for Register VIDEOSYSC_IRQSTATE
IVA2.2 Subsystem Functional Description
• Video Accelerator/Sequencer SYSC : [0] [1] [2] [3]
IVA2.2 Subsystem Basic Programming Model
• Video and Sequencer Module interrupt Handling : [4]
IVA2.2 Subsystem Register Manual
• Video System Controller Register Mapping Summary : [5]
• Video System Controller Register Descriptions : [6] [7] [8]
Table 5-704. VIDEOSYSC_CLKCTL
Address Offset 0x0000 0060
Physical Address 0x0009 C060 Instance VIDEOSYSC
Description Video accelerator clock control: Writing a 0 forces the module to leave the idle state (modules input clock goes
active) Writing a 1 requests the module enter the idle state when no request/commands pending for the module.
(Allows module input clock to be stopped). Module automatically exits the idle state and clock starts each time
new requests/commands are present. Clock status can be checked in
VIDEOSYSC_CLKST register
Type W
Bits Field Name Description Type Reset
31:6 RESERVED Reserved W 0x0
Read returns 0
5 SL2IFCLKEN Clock control of the SL2IF module W 0x0
(iLF and iME modules must be idled as well):
0: Exit idle state and start SL2IF clock
1: Request SL2IF logic to go to idle and stop SL2IF input clock
4 SEQMEMCLKEN Clock control of the sequencer memory and slave port module: W 0x0
0: Exit idle state and start SEQ memory and slave port clock
1: Request SEQ slave port logic to go to idle and stop SEQ
clock (if SEQ in standby)
3 RESERVED Reserved W 0x0
Read returns 0
2 IVLCDCLKEN Clock control of the iVLCD module: W 0x0
0: Exit idle state and start iVLCD clock
1: Request iVLCD logic to go to idle and stop iVLCD input clock
1 iMECLKEN Clock control of the iME module: W 0x0
0: Exit idle state and start iME clock
1: Request iME logic to go to idle and stop iME input clock
1054 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
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