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Interrupt Controller Basic Programming Model
12.5.4 MPU INTC Spurious Interrupt Handling
The spurious flag indicates whether the result of the sorting (a window of 10 INTC functional clock cycles
after the interrupt assertion) is invalid. The sorting is invalid if:
•
The interrupt that triggered the sorting is no longer active during the sorting.
•
A change in the mask has affected the result during the sorting time.
As a result, the values in the MPU_INTC.
, or
MPU_INTC.
registers must not be changed while the corresponding interrupt is
asserted. If these registers are changed within the 10-cycle window after the interrupt assertion, only the
active interrupt input that triggered the sort can be masked before its turn in the sort. The resulting values
of the following registers become invalid:
•
•
•
•
MPU_INTC.
This condition is detected for both IRQ and FIQ, and the invalid status is flagged across the
SPURIOUSIRQFLAG (see Note 1) and SPURIOUSFIQFLAG (see Note 2) bit fields in the SIR and
PRIORITY registers. A 0 indicates valid and a 1 indicates invalid interrupt number and priority. The invalid
indication can be tested in software as a false register value.
NOTE:
1.
The MPU_INTC.
[31:7] SPURIOUSIRQFLAG bit field is a copy of the
[31:7] SPURIOUSIRQFLAG bit field.
2.
The MPU_INTC.
[31:7] SPURIOUSFIQFLAG bit field is a copy of the
[31:7] SPURIOUSFIQFLAG bit field.
2421
SWPU177N – December 2009 – Revised November 2010
Interrupt Controller
Copyright © 2009–2010, Texas Instruments Incorporated
