Texas Instruments OMAP36 Series, Technical Reference Manual

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Interrupt Controller Register Manual
Table 12-22. INTCPS_IDLE
Address Offset 0x050
Physical Address 0x4820 0050 Instance MPU INTC
0x480C 8050 Modem INTC
Description This register controls the functional clock auto-idle and the synchronizer clock auto-gating.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
TURBO
FUNCIDLE
Bits Field Name Description Type Reset
31:2 Reserved Write 0s for future compatibility. Read returns reset R 0x00000000
value.
1 TURBO Input synchronizer clock auto-gating RW 0
0x0: Input synchronizer clock is free-running
(default).
0x1: Input synchronizer clock is auto-gated based
on interrupt input activity.
0 FUNCIDLE Functional clock idle mode RW 0
0x0: Functional clock gating strategy is applied
(default).
0x1: Functional clock is free-running.
Table 12-23. Register Call Summary for Register INTCPS_IDLE
Interrupt Controller Functional Description
• Module Power Saving : [0] [1] [2]
• Interrupt Latency : [3] [4]
Interrupt Basic Programming Model
• Initialization Sequence : [5]
Interrupt Controller Register Manual
• Register Summary : [6]
Table 12-24. INTCPS_IRQ_PRIORITY
Address Offset 0x060
Physical Address 0x4820 0060 Instance MPU INTC
Description This register supplies the currently active IRQ priority level.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPURIOUSIRQFLAG IRQPRIORITY
Bits Field Name Description Type Reset
31:6 SPURIOUSIRQFLAG Spurious IRQ flag R 0x3FFFFFF
5:0 IRQPRIORITY Current IRQ priority R 0x00
2427 SWPU177N – December 2009 – Revised November 2010 Interrupt Controller
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