Texas Instruments OMAP36 Series, Technical Reference Manual

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Interrupt Controller Basic Programming Model
12.5 Interrupt Controller Basic Programming Model
12.5.1 Initialization Sequence
1. Program the MPU_INTC. INTCPS_SYSCONFIG register: If necessary, enable the interface clock
autogating by setting the AUTOIDLE bit.
2. Program the MPU_INTC. INTCPS_IDLE register: If necessary, disable functional clock autogating or
enable synchronizer autogating by setting the FUNCIDLE bit or TURBO bit accordingly.
3. Program the MPU_INTC. INTCPS_ILRm register for each interrupt line: Assign a priority level and set
the FIQNFIQ bit for an FIQ interrupt (by default, interrupts are mapped to IRQ and priority is 0x0
[highest]).
4. Program the MPU_INTC. INTCPS_MIRn register: Enable interrupts (by default, all interrupt lines are
masked).
NOTE: To program the MPU_INTC. INTCPS_MIRn register, the MPU_INTC. INTCPS_MIR_SETn
and MPU_INTC. INTCPS_MIR_CLEARn registers are provided to facilitate the masking, even
if it is possible for backward-compatibility to write directly to the MPU_INTC. INTCPS_MIRn
register.
12.5.2 MPU INTC Processing Sequence
After the MPU_INTC. INTCPS_MIRn and MPU_INTC. INTCPS_ILRm registers are configured to enable
and assign priorities to incoming interrupts, the interrupt is processed as explained in the following
subsections.
IRQ and FIQ processing sequences are quite similar, the differences for the FIQ sequence are shown
after a '/' character in bold characters in the text or the code below.
1. One or more unmasked incoming interrupts (M_IRQ_n signals) are received and IRQ or FIQ outputs
(MPU_INTC_IRQ/FIQ) are not currently asserted.
2. If the MPU_INTC. INTCPS_ILRm [0] FIQNIRQ bit is set to 0, the MPU_INTC_IRQ output signal is
generated. If the FIQNIRQ bit is set to 1, the MPU_INTC_FIQ output signal is generated.
3. The INTC performs the priority sorting and updates the MPU_INTC. INTCPS_SIR_IRQ [6:0]
ACTIVEIRQ /MPU_INTC. INTCPS_SIR_FIQ [6:0] ACTIVEFIQ field with the current interrupt number.
4. During priority sorting, if the IRQ/FIQ is enabled at the host processor side, the host processor
automatically saves the current context and executes the ISR as follows:
NOTE: The ARM host processor automatically performs the following actions in pseudo code.
LR = PC + 4 /* return link */ SPSR = CPSR /* Save CPSR before execution */ CPSR[5] = 0 /*
Execute in ARM state */ CPSR[7] = 1 /* Disable IRQ */ CPSR[8] = 1 /* Disable Imprecise Data
Aborts */ CPSR[9] = CP15_reg1_EEbit /* Endianness on exception entry */ if interrupt == IRQ
then CPSR[4:0] = 0b10010 /* Enter IRQ mode */ if high vectors configured then PC = 0xFFFF0018
else PC = 0x00000018 /* execute interrupt vector */ else if interrupt == FIQ then CPSR[4:0] =
0b10001 /* Enter FIQ mode */ CPSR[6] = 1 /* Disable FIQ */ if high vectors configured then PC
= 0xFFFF001C else PC = 0x0000001C /* execute interrupt vector */ endif
5. The ISR saves the remaining context, identifies the interrupt source by reading the
ACTIVEIRQ/ACTIVEFIQ field, and jumps to the relevant subroutine handler as follows:
CAUTION
The code in steps 5 and 7 is an assembly code compatible with ARM
architecture V6 and V7. This code is developed for the Texas Instruments Code
Composer Studio tool set. It is a draft version, only tested on an emulated
environment.
/* INTCPS_SIR_IRQ/INTCPS_SIR_FIQ register address INTCPS_SIR_IRQ_ADDR/INTCPS_SIR_FIQ_ADDR
.word 0x48200040/0x48200044 /* ACTIVEIRQ bit field mask to get only the bit field
2415 SWPU177N – December 2009 – Revised November 2010 Interrupt Controller
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