Texas Instruments OMAP36 Series, Technical Reference Manual

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Interrupt Controller Register Manual
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Table 12-34. INTCPS_MIR_CLEARn
Address Offset 0x088 + (0x20 * n) Index n = 0 to 2
Physical Address 0x4820 0088 + (0x20 * n) Instance MPU INTC
Description This register is used to clear the interrupt mask bits.
Type W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIRCLEAR
Bits Field Name Description Type Reset
31:0 MIRCLEAR W 0x00000000
Clear the interrupt mask bits. Read returns 0.
Write
Clears the MIR mask bit to 0
0x1:
Write
No functional effect
0x0:
Table 12-35. Register Call Summary for Register INTCPS_MIR_CLEARn
Interrupt Basic Programming Model
• Initialization Sequence : [0]
Interrupt Controller Register Manual
• Register Summary : [1]
Table 12-36. INTCPS_MIR_SETn
Address Offset 0x08C + (0x20 * n) Index n = 0 to 2
Physical Address 0x4820 008C + (0x20 * n) Instance MPU INTC
Description This register is used to set the interrupt mask bits.
Type W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIRSET
Bits Field Name Description Type Reset
31:0 MIRSET W 0x00000000
Mask the interrupt bits. Read returns 0.
Write
No functional effect
0x0:
Write
Sets the MIR mask bit to 1.
0x1:
Table 12-37. Register Call Summary for Register INTCPS_MIR_SETn
Interrupt Basic Programming Model
• Initialization Sequence : [0]
• MPU INTC Spurious Interrupt Handling : [1]
Interrupt Controller Register Manual
• Register Summary : [2]
2430 Interrupt Controller SWPU177N – December 2009 – Revised November 2010
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