Public Version
Interrupt Controller Functional Description
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Once the interrupting peripheral device has been serviced and the incoming interrupt deasserted, the user
must write to the appropriate NEWIRQAGR or NEWFIQAGR bit to indicate to the INTCPS the interrupt
has been handled. If there are any pending unmasked incoming interrupts for this interrupt request type,
the INTCPS restarts the appropriate priority sorter; otherwise, the IRQ or FIQ interrupt line is deasserted.
12.4.2 Register Protection
If the MPU_INTC.
[0] PROTECTION bit is set, access to the INTCPS registers is
restricted to the supervisor mode. Access to the MPU_INTC.
register is always
restricted to privileged mode.
12.4.3 Module Power Saving
The INTCPS provides an auto-idle function in its three clock domains:
•
Interface clock
•
Functional clock
•
Synchronizer clock
The interface clock auto-idle power-saving mode is enabled if the MPU_INTC.
AUTOIDLE bit is set to 1. When this mode is enabled and there is no activity on the bus interface, the
interface clock is disabled internally to the module, thus reducing power consumption. When there is new
activity on the bus interface, the interface clock restarts without any latency penalty. After reset, this mode
is disabled, by default.
The functional clock auto-idle power-saving mode is enabled if the MPU_INTC.
FUNCIDLE bit is set to 0. When this mode is enabled and there is no active interrupt (IRQ or FIQ interrupt
being processed or generated) or no pending incoming interrupt, the functional clock is disabled internally
to the module, thus reducing power consumption. When a new unmasked incoming interrupt is detected,
the functional clock restarts and the INTCPS processes the interrupt. If this mode is disabled, the interrupt
latency is reduced by one cycle. After reset, this mode is enabled, by default.
The synchronizer clock allows external asynchronous interrupts to be resynchronized before they are
masked. The synchronizer input clock has an auto-idle power-saving mode enabled if the
MPU_INTC.
[1] TURBO bit is set to 1. If the auto-idle mode is enabled, the standby power is
reduced, but the IRQ or FIQ interrupt latency increases from four to six functional clock cycles. This
feature can be enabled dynamically according to the requirements of the device. After reset, this mode is
disabled, by default.
To reduce power consumption of the modem INTC, which is not use in the stand-alone device, modem
INTC clocks must be configured in auto-idle mode. Therefore, both the
MPU_INTC.
[1] TURBO bits must be
set to 1 during initialization.
12.4.4 Interrupt Latency
The IRQ/FIQ interrupt generation takes four INTCPS functional clock cycles (plus or minus one cycle) if
the MPU_INTC.
[1] TURBO bit is set to 0. If the TURBO bit is set to 1, the interrupt
generation takes six cycles, but power consumption is reduced while waiting for an interrupt.
These latencies can be reduced by one cycle by disabling functional clock auto-idle
(MPU_INTC.
[0] FUNCIDLE bit set to 1), but power consumption is increased, so the benefit
is minimal. For information about power saving, see
To minimize interrupt latency when an unmasked interrupt occurs, the IRQ or FIQ interrupt is generated
before priority sorting completion. The priority sorting takes 10 functional clock cycles, which is less than
the minimum number of cycles required for the MPU to switch to the interrupt context after reception of the
IRQ or FIQ event.
Any read of the MPU_INTC.
or MPU_INTC.
register during the
priority sorting process stalls until priority sorting is complete and the relevant register is updated.
However, the delay between the interrupt request being generated and the interrupt service routine being
executed is such that priority sorting always completes before the MPU_INTC.
or
MPU_INTC.
register is read.
2414
Interrupt Controller
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
