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SDMA Basic Programming Model
11.5.4 Synchronized Transfer Monitoring Using CDAC
The
register is writable and non-initialized during reset (value undefined). It can be
initialized to monitor a transfer by applying the following programming model:
1. Write 0 in
2. Enable the channel.
3. If timeout occurs, read
4. If
!= 0 (it is the value configured in
):
This indicates that the corresponding transfer has started. User can then rely on
and
element and frame counters.
Else, if
= 0 (it is the value configured in the
This indicates that the corresponding transfer did not start.
11.5.5 Concurrent Software and Hardware Synchronization
This section describes thread allocation only, not the entire transfer. Because synchronized transfers are
latency critical, you must allocate a thread on the synchronized target side at least.
Even for multiple concurrent channels, thread reservation guarantees that as soon as an HW DMA
request comes in, the read/write scheduler finds available thread(s) to initiate a channel schedule and
issue a read/write transaction.
Consider these six concurrent channels:
•
Channels 0/1/2/3 are dedicated to memory-memory transfer: they are software triggered and not
synchronized.
•
Channel 4 is dedicated to memory
→
peripheral transfer, hardware triggered, and synchronized on the
write side.
•
Channel 5 is dedicated to peripheral
→
memory transfer, hardware triggered, and synchronized on the
read side.
1. Allow thread reservation for priority channel 4 and channel 5:
Reserve one thread (Read ThreadID 0) on the read port: Set
[13:12] = 0x1.
Reserve one thread (Write ThreadID 0) on the write port: Set
[13:12] = 0x1.
2. Specify channel priority:
Channel 4 is a write high priority channel: Set
[26] = 1.
Channel 5 is a read high priority channel: Set
[6] = 1.
11.5.6 Chained Transfer
A chained DMA transfer can be programmed as follows:
1. Configure the transfer parameters for each logical DMA channel in the chain as in step 1 for either the
synchronized or non-synchronized transfers above.
2. For each channel in the chain, configure the
register as follows:
•
Next logical DMA channel number (for a looping chained transfer link last channel to first channel
number), in DMA register bits
[4:0].
•
Include the logical channel to the chain and enable link by setting the DMA register bit
[15].
•
For a non-looping chain, the last logical channel in the chain must have the DMA register bit
[15] set to 0 to indicate the end of the chain.
3. Enable the transfer via the enable bit in the first logical channel DMA register bit
[7]. All
other channels in the chain must be configured as disabled. Each channel is enabled automatically in
turn when the previous logical channel transfer completes. A non-synchronized transfer starts
immediately; a hardware-synchronized transfer starts when the DMA request line corresponding to the
first DMA channel in the chain is asserted.
To stop a looping chained transfer, disable the
[15] ENABLE_LNK bit (by setting it to
0x0), of the final channel transfer.
2371
SWPU177N – December 2009 – Revised November 2010
SDMA
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