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SDMA Basic Programming Model
<< 6)); RegVal = ((RegVal & ~(0x1 << 13)) | (DMA4->DestinationPacked << 13)); // Write CSDP
DMA4_CSDP_CH10 = RegVal; /* b) Set the number of element per frame CEN[23:0]*/ DMA4_CEN_CH10 =
DMA4->NumberOfElementPerFrame; /* c) Set the number of frame per block CFN[15:0]*/ DMA4_CFN_CH10
= DMA4->NumberOfFramePerTransferBlock; /* d) Set the Source/dest start address index
CSSA[31:0]/CDSA[31:0]*/ DMA4_CSSA_CH10 = DMA4->SourceStartAddress; // address start
DMA4_CDSA_CH10 = DMA4->DestinationStartAddress; // address dest /* e) Set t1he Read Port
adressing mode CCR[13:12], the Write Port adressing mode CCR[15:14], read/write priority
CCR[6]/CCR[26], the current LCH CCR[20:19]=00 and CCR[4:0]=00000*/ // Read CCR RegVal =
DMA4_CCR_CH10; // Build reg RegVal = ((RegVal & ~(0x3 << 12)) | (DMA4->ReadPortAccessMode <<
12)); RegVal = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessMode << 14)); RegVal = ((RegVal &
~(0x1 << 6)) | (DMA4->ReadPriority << 6)); RegVal = ((RegVal & ~(0x1 << 26)) | (DMA4-
>WritePriority << 26)); RegVal&= 0xFFCFFFE0 ; // Write CCR DMA4_CCR_CH10 = RegVal; /* f)- Set the
source element index CSEI[15:0]*/ DMA4_CSEI_CH10 = DMA4->SourceElementIndex; /* - Set the source
frame index CSFI[15:0]*/ DMA4_CSFI_CH10 = DMA4->SourceFrameIndex ; /* - Set the destination
element index CDEI[15:0]*/ DMA4_CDEI_CH10 = DMA4->DestinationElementIndex; /* - Set the
destination frame index CDFI[31:0]*/ DMA4_CDFI_CH10 = DMA4->DestinationFrameIndex; /* 2) Start
the DMA transfer by Setting the enable bit CCR[7]=1 */ /*-----------------------------------------
---------------------*/ //write enable bit DMA4_CCR_CH10 |= 1 << 7; /* start */
11.5.3 Hardware-Synchronized Transfer
To monitor a hardware synchronized DMA transfer, initialize the
register before the
software enable.
To configure an LCh to synchronize by element, packet, frame, or block, the frame synchronization
[5] FS bit and the block synchronization
[18] BS bit register must be
programmed. For all the following synchronized transfers (element, packet, frame or block synchronized
transfers) User must set first :
[24] SEL_SRC_DST_SYNC to 1 when the source triggers on
the DMA request and
[24] SEL_SRC_DST_SYNC to 0 when the Destination triggers on the
DMA request. Note: User must take care when setting the
[23] PREFETCH bit it is in
conjunction with
[24] SEL_SRC_DST_SYNC bit .
•
To configure an LCh to transfer one element per DMA request:
1. Set the number of DMA request associated to the current LCH in the
SYNCHRO_CONTROL_UPPER and
[4:0] SYNCHRO bit field.
2. Set the data type, also referenced as element size (ES), in the
[1:0] DATA_TYPE bit
field.
3. Set the Read Port access type (single or burst access) in the
[8:7] SRC_BURST_EN bit
field.
4. Set the Write Port access type (single or burst access) in the
[15:14] DST_BURST_EN
bit field.
5. Set the Read Port addressing mode in the
[13:12] SRC_AMODE bit field.
6. Set the Write Port addressing mode in the
[15:14] DST_AMODE bit field.
7. Set the Read start address in the
[31:0] SRC_START_ADRS bit field.
8. Set the Write start address in the
[31:0] DST_START_ADRS bit field.
9. Set both FS and BS to 0 in
[5] FS and
[18] BS.
10. Set to 1 the channel enable bit
[7] EN bit.
•
To configure an LCh to transfer one frame per DMA request:
1. Set the number of DMA request associated to the current LCH in the
SYNCHRO_CONTROL_UPPER and
[4:0] SYNCHRO bit field.
2. Set the data type, also referenced as element size (ES), in the
[1:0] DATA_TYPE bit
field.
3. Set the number of element per frame in the
[23:0] CHANNEL_ELMNT_NBR bit field.
4. Set the Read Port access type (single or burst access) in the
[8:7] SRC_BURST_EN bit
field.
5. Set the Write Port access type (single or burst access) in the
[15:14] DST_BURST_EN
bit field.
6. Set the Read Port addressing mode in the
[13:12] SRC_AMODE bit field.
7. Set the Write Port addressing mode in the
[15:14] DST_AMODE bit field.
2369
SWPU177N – December 2009 – Revised November 2010
SDMA
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