Public Version
SDMA Functional Description
www.ti.com
Both features support 8 bpp (bits per pixel), 16 bpp, and 24 bpp, depending on what is specified as the
DMA transfer ES via the
register. An ES of 32 bits corresponds to 24 bpp. During a 32-bit
(24 bpp) transfer, the most-significant 8 bits ([31:24]) are 0. Both features are compatible with packed and
burst transactions.
11.4.15 Supervisor Modes
A logical DMA channel can be configured to operate in supervisor mode through the corresponding bits in
the channel
register. This must be done using supervisor access. Once a channel is
configured in supervisor mode, the channel configuration is protected from nonsupervisor accesses. All
DMA transactions on a supervisor channel are supervisor transactions.
11.4.16 Posted and Nonposted Writes
A logical channel can be configured in its DMA register bits
[17:16] to use one of three write
access handshake modes for the destination:
•
Nonposted write: Each write must complete before transfer can continue or complete.
•
Posted write: Transfer continues without waiting for each write to complete (might improve
performance with slow devices).
•
Posted with final write nonposted: Transfer continues without waiting for each write to complete, but
final write is completed before transfer can complete.
11.4.17 Disabling a Channel During Transfer
When a channel is disabled during a transfer, the channel will undergo an abort, except if the channel was
hardware source synchronized with buffering Enabled (
[25] BUFFERING_DISABLE='0'). In
that case, the fifo will be drained in order to avoid losing data. See
for details on this
feature.
11.4.18 FIFO Draining Mechanism
When a source synchronized channel is disabled during a transfer, then the current hardware request
(element/packet/frame/block) service is completed and the channel
[9] RD_ACTIVE bit is set
to 0, which means the channel is not active on the read port. The remaining data in the corresponding
disabled channel FIFO is drained onto the write port and transferred to the programmed destination as in
normal transfer.
At the end of the draining the
[10] WR_ACTIVE bit is set to 0 (channel is no more active on
the write port) and if the
[12] DRAIN_END_IE is set to 1, the status bit
DRAIN_END is updated and an interrupt is generated.
Once a channel is disabled during a transfer, it needs to wait for
[9] RD_ACTIVE and
[10] WR_ACTIVE to become '0' before being re-enabled for a new transfer. The FIFO drain
for a channel will happen only in the following cases:
•
If the channel is a source synchronized channel and
[25] BUFFERING_DISABLE='0' and
•
If the channel is not a solid fill channel and
•
If the channel is not a transparent and copy channel
NOTE:
In case of a self-linked or chain-linked channel, it is user responsibility to disable the
[15] ENABLE_LINK bit before disabling the channel.
In all other cases, the channel will undergo an abort.
2360
SDMA
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
