Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1383 / 3738

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Camera ISP Register Manual
Bits Field Name Description Type Reset
2:0 LOFST3 Line offset values of odd lines and odd fields RW 0x0
(field id = 1).
This bit field is latched by the VS sync pulse.
0x0: +1 line
0x1: +2 lines
0x2: +3 lines
0x3: +4 lines
0x4: -1 line
0x5: -2 lines
0x6: -3 lines
0x7: -4 lines
Table 6-232. Register Call Summary for Register CCDC_SDOFST
Camera ISP Functional Description
• Camera ISP CCDC Functional Operations : [0] [1] [2] [3] [4] [5] [6] [7]
Camera ISP Basic Programming Model
• Camera ISP CCDC Register Setup : [8]
• Camera ISP CCDC Register Accessibility During Frame Processing : [9]
• Camera ISP CCDC Image-Signal Processing : [10]
Camera ISP Register Manual
• Camera ISP CCDC Register Summary : [11]
Table 6-233. CCDC_SDR_ADDR
Address Offset 0x0000 002C
Physical Address 0x480B C62C Instance ISP_CCDC
Description MEMORY ADDRESS REGISTER
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
Bits Field Name Description Type Reset
31:0 ADDR Memory address RW 0x00000000
Sets the CCDC module output address. The address
should be aligned on a 32-byte boundary: the 5 least
significant bits are ignored.
For optimal performance in the system, the address must
be on a 256-byte boundary.
This bit field is latched by the VS sync pulse.
Table 6-234. Register Call Summary for Register CCDC_SDR_ADDR
Camera ISP Functional Description
• Camera ISP CCDC Functional Operations : [0] [1]
Camera ISP Basic Programming Model
• Camera ISP CCDC Register Setup : [2]
• Camera ISP CCDC Register Accessibility During Frame Processing : [3]
• Camera ISP CCDC Image-Signal Processing : [4]
Camera ISP Register Manual
• Camera ISP CCDC Register Summary : [5]
1383 SWPU177N – December 2009 – Revised November 2010 Camera Image Signal Processor
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