HS
V
S
Effective pixels
ouput to memory
CCDC_HORZ_INFO[14:0]
NPH
CCDC
_VE
R
T_L
INES
[14
:0]
NL
V
CCDC_HORZ_INFO[30:16]
SPH
CC
DC_V
ER
T_
S
T
A
R
T
SL
Vx(
x=
0:
1)
camisp-119
Public Version
www.ti.com
Camera ISP Basic Programming Model
Figure 6-118. Camera ISP CCDC Clipping Window Before Output to Memory
6.5.6.6.2.6.6 Camera ISP CCDC Output to Memory
The output formatter memory write enable is controlled by the
[17] WEN bit. The
output of the data reformatter can be written to memory by setting
[18] VP2SDR to 1.
The pixel data at the output of the output formatter is written to the address given by the
register. The address should be aligned on a 32-byte boundary. The 5 LSBs are
ignored. Reading the register always shows the 5 LSBs as 0.
A destination pitch can be set with the
register. The offset must be a multiple of 32
bytes. The 5 LSBs are ignored. Reading the register always shows the 5 LSBs as 0. It is required for the
pixel line length to be a multiple of 32 bytes to be stored in memory without holes.
The
register controls how the pixels are stored to memory.
Data to be written to memory can be qualified by the external cam_wen signal. This feature can be
enabled by setting the
[5] EXWEN bit. The
[8] WENLOG bit configures
how the cam_wen signal is used with the internally generated valid signal.
The data can be swapped on a byte basis with the
[12] BSWD bit.
If
[13:12] INPMOD = 1, the MSB of the 8-bit chroma component can be inverted by
setting
[13] MSBINVI to 1.
1279
SWPU177N – December 2009 – Revised November 2010
Camera Image Signal Processor
Copyright © 2009–2010, Texas Instruments Incorporated