Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1278 / 3738

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8 bits packed
8 bits
9 bits
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pix3 pix 2 pix 1 pix 0
pix 0
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pix 0 pix 1
pix 0
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pix 1
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camisp-118
Public Version
Camera ISP Basic Programming Model
www.ti.com
6.5.6.6.2.6.4 Camera ISP CCDC Data Packing
Pixel data are stored to memory in little-endian format (bytes at lower addresses have lower significance).
By default, pixel data are stored in 16-bit words; unused bits are filled with zeros.
If the input data is 8 bits, or if A-Law compression is enabled, the data can be stored in 8-bit words by
setting the
CCDC_SYN_MODE [11] PACK8 bit to 1.
If the input data is 12, 11, 10, or 9 bits, and A-Law compression is not enabled, the 8 MSBs are stored to
memory.
Figure 6-117 shows data packing and pixel ordering.
Figure 6-117. Camera ISP CCDC Data Packing - Pixel Ordering
6.5.6.6.2.6.5 Camera ISP CCDC Clipping Window
Before data is stored in memory, a clipping window can be set; only a selected sensor area is stored to
memory.
Figure 6-118 shows the settings; only the white area is stored to memory.
• The valid-data horizontal start position is controlled with the CCDC_HORZ_INFO [30:16] SPH bit field.
The valid-data vertical start position is controlled with the CCDC_VERT_START register. If the sensor
is interlaced, the vertical start position for even and odd fields can be configured independently with the
CCDC_VERT_START register. If the sensor is progressive, the CCDC_VERT_START [14:0] SLV1 bit
field is ignored.
• The valid-data horizontal size is controlled with the CCDC_HORZ_INFO [14:0] NPH bit field. The
horizontal size must be a multiple of 16 pixels. The valid-data vertical size is controlled with the
CCDC_VERT_LINES [14:0] NLV register.
1278 Camera Image Signal Processor SWPU177N – December 2009 – Revised November 2010
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