Texas Instruments OMAP36 Series, Technical Reference Manual

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Camera ISP Basic Programming Model
• SYNC mode:
– In this mode, the input data can be either raw data or YCbCr data. Setting
CCDC_SYN_MODE .INPMODE = 0 selects raw data, and CCDC_SYN_MODE [13:12] INPMODE =
1 or 2 selects YCbCr data on 16 or 8 bits. If CCDC_SYN_MODE [13:12] INPMODE = 0, the cam_d
signal width is selected through CCDC_SYN_MODE [10:8] DATSIZ: the possible values are 8, 10,
11, and 12 bits.
– If CCDC_SYN_MODE [13:12] INPMODE = 1, the cam_d signal width is 8 bits, but the internal
CCDC module data path is configured to 16 bits. It is mandatory to enable the 8- to 16-bit bridge by
setting
ISP_CTRL [3:2] PAR_BRIDGE = 2 or 3. The ISP_CTRL [3:2] PAR_BRIDGE bit also controls
how the 8-bit data is mapped onto the 16-bit data.
– The value set in CCDC_SYN_MODE [10:8] DATSIZ does not matter. The position of the Y
component can be set with the CCDC_CFG [11] Y8POS bit.
– If CCDC_SYN_MODE [13:12] INPMODE = 2, the cam_d signal width is 8 bits. The value set in
CCDC_SYN_MODE [10:8] DATSIZ does not matter. The position of the Y component can be set
with the CCDC_CFG [11] Y8POS bit.
– The internal timing generator must be enabled with CCDC_SYN_MODE [16] VDHDEN = 1.
• ITU mode:
– In this mode, the data follows the protocol set by the ITU-R BT.656 protocol. To select it, set
CCDC_REC656IF [0] R656ON = 1. When this mode is selected, the values set in
CCDC_SYN_MODE [13:12] INPMODE and CCDC_SYN_MODE [10:8] DATSIZ do not matter.
– To select the 8-bit or 10-bit protocol, set the CCDC_CFG [5] BW656 bit field. Data line cam_d [7:0]
are used for 8-bit YCbCr and cam_d[9:0] are used for 10-bit YCbCr.
– FVH error correction is enabled by setting CCDC_REC656IF [1] ECCFVH = 1.
– The internal timing generator must be enabled with CCDC_SYN_MODE [16] VDHDEN = 1.
6.5.6.6.1.2 Camera ISP CCDC Timing Generator and Frame Settings
The polarities of the cam_hs, cam_vs, and cam_fld signals are controlled by the CCDC_SYN_MODE [3]
HDPOL, CCDC_SYN_MODE [2] VDPOL, and CCDC_SYN_MODE [4] FLDPOL bit fields. The polarities can
be positive or negative.
The pixel data is presented on cam_d one pixel for every cam_pclk rising edge or falling edge. It is
controlled with the
ISP_CTRL [4] PAR_CLK_POL bit.
The CCDC_SYN_MODE [7] FLDMODE bit fields set the image-sensor type to progressive or interlaced
mode. When the sensor is interlaced, the CCDC_SYN_MODE [15] FLDSTAT status bit indicates whether
the current frame is odd or even.
The polarity of the cam_d signal can also be controlled with the CCDC_SYN_MODE [6] DATAPOL bit field.
The polarity can be normal mode or ones complement mode.
Furthermore, the directions of the cam_fld and cam_hs/cam_vs signals are controlled by the
CCDC_SYN_MODE [1] FLDOUT and CCDC_SYN_MODE [0] VDHDOUT bits. If CCDC_SYN_MODE [0]
VDHDOUT is set as an output, the CCDC_PIX_LINES register controls the length of the cam_hs and
cam_vs signals.
If CCDC_SYN_MODE [0] VDHDOUT = 1:
• The HS sync pulse width is given by CCDC_HD_VD_WID [27:16] HDW. The VS sync pulse width is
given by CCDC_HD_VD_WID [11:0] VDW.
• The HS period is given by CCDC_PIX_LINES [31:16] PPLN. The VS period is given by
CCDC_PIX_LINES [15:0] HLPRF x 2.
Figure 6-115 shows the HS/VS sync pulse output timings.
1271 SWPU177N – December 2009 – Revised November 2010 Camera Image Signal Processor
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