Texas Instruments OMAP36 Series, Technical Reference Manual

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Camera ISP Basic Programming Model
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6.5.6.2 Camera ISP CCDC Enable/Disable Hardware
All required registers mentioned in the previous section must be programmed before setting the
CCDC_PCR [0] ENABLE bit.
The CCDC always operates in continuous mode. In other words, after enabling the CCDC, it processes
sequential frames until the ENABLE bit is cleared by software. When this happens, the frame being
processed completes before the CCDC is disabled.
When the CCDC is in master mode (HS/VS signals set to outputs), fetching and processing of the frame
begin immediately on setting the
CCDC_PCR [0] ENABLE bit.
When the CCDC is in slave mode (HS/VS signals set to inputs), processing of the frame depends on the
input timing of the external sensor/decoder. To ensure that data from the external device is not missed,
the CCDC must be enabled before data transmission from the external device. In this way, the CCDC
waits for data from the external device.
On setting the CCDC_FPC [15] FPCEN bit, the CCDC begins to fetch and buffer the faulty-pixel table from
memory. If faulty-pixel correction is used, the CCDC_FPC [15] FPCEN bit must be set before the
CCDC_PCR [0] ENABLE bit, but after the faulty-pixel table is placed in memory and the CCDC_FPC [14:0]
FPNUM and CCDC_FPC_ADDR registers are set.
6.5.6.3 Camera ISP CCDC Events and Status Checking
The CCDC can generate three different interrupts: CCDC_VD0_IRQ, CCDC_VD1_IRQ, and
CCDC_VD2_IRQ.
The CCDC_SYN_MODE [16] VDHDEN bit must be enabled to receive any of the CCDC CCDC_VDx_IRQ
interrupts.
6.5.6.3.1 Camera ISP CCDC Interrupts
The CCDC module has three programmable events: CCDC_VD0_IRQ, CCDC_VD1_IRQ, and
CCDC_VD2_IRQ, and one error event CCDC_ERR_IRQ. Event generation is described in
Section 6.5.6.3.2 , CCDC_VD0_IRQ and CCDC_VD1_IRQ Interrupts, and Section 6.5.6.3.3 ,
CCDC_VD2_IRQ Interrupt.
CCDC module events can be mapped to the ARM or the DSP:
•
The CCDC_VD0_IRQ, CCDC_VD1_IRQ, CCDC_VD2_IRQ, and CCDC_ERR_IRQ bits in the
ISP_IRQ0ENABLE register control whether the CCDC module events trigger an interrupt to the ARM.
The ISP_IRQ0STATUS register indicates which event(s) triggered the interrupt. An event is cleared by
writing a 1 in its corresponding bit in the ISP_IRQ0STATUS register. To clear the CCDC_ERR_IRQ
interrupt, clear the CCDC_FPC [16] FPERR bit before clearing the ISP_IRQ0STATUS [11]
CCDC_ERR_IRQ bit.
• The CCDC_VD0_IRQ, CCDC_VD1_IRQ, CCDC_VD2_IRQ, and CCDC_ERR_IRQ bits in the
ISP_IRQ1ENABLE register control whether the CCDC module events trigger an interrupt to the DSP.
The ISP_IRQ1STATUS register indicates which event(s) triggered the interrupt. An event is cleared by
writing a 1 in its corresponding bit in the ISP_IRQ1STATUS register. To clear the CCDC_ERR_IRQ
interrupt, clear the CCDC_FPC [16] FPERR bit before clearing the ISP_IRQ1STATUS [11]
CCDC_ERR_IRQ bit.
6.5.6.3.2 Camera ISP CCDC CCDC_VD0_IRQ and CCDC_VD1_IRQ Interrupts
As shown in Figure 6-112 , the CCDC_VD0_IRQ and CCDC_VD1_IRQ interrupts occur relative to the VS
pulse. The trigger timing is selected by using the CCDC_SYN_MODE [2] VDPOL setting. CCDC_VD0_IRQ
and CCDC_VD1_IRQ occur after receiving the number of horizontal lines (HS pulse signals) set in the
CCDC_VDINT [30:16] VDINT0 and CCDC_VDINT [14:0] VDINT1 register fields, respectively.
NOTE: In the case of BT.656 input mode, there is VS at the beginning of each field. Therefore,
there are two interrupts for each frame (one for each field).
1268 Camera Image Signal Processor SWPU177N – December 2009 – Revised November 2010
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