Texas Instruments OMAP36 Series, Technical Reference Manual

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Camera ISP Integration
Table 6-17. Camera ISP CSI1/CCP2B Receiver Interrupt Details (continued)
Event Mask Description
CCP2_LC23_IRQSTATUS [9] CCP2_LC23_IRQENABLE [9] LC2_LS_IRQ Line-start synchronization code detection for
LC2_LS_IRQ logical channel 2:
This interrupt is triggered on the detection of a
line-start synchronization code into the CCP2 data
stream.
CCP2_LC23_IRQSTATUS [8] CCP2_LC23_IRQENABLE [8] LC2_FE_IRQ Frame-end synchronization code detection for
LC2_FE_IRQ logical channel 2:
This interrupt is triggered on the detection of a
frame-end synchronization code into the CCP2
data stream.
CCP2_LC23_IRQSTATUS [7] CCP2_LC23_IRQENABLE [7] Frame counter reached for logical channel 2:
LC2_COUNT_IRQ LC2_COUNT_IRQ This interrupt is triggered on the frame counter
reached into the CCP2 data stream.
CCP2_LC23_IRQSTATUS [5] CCP2_LC23_IRQENABLE [5] FIFO overflow error for logical channel 2:
LC2_FIFO_OVF_IRQ LC2_FIFO_OVF_IRQ This interrupt is triggered on the detection of a
FIFO overflow error.
CCP2_LC23_IRQSTATUS [4] CCP2_LC23_IRQENABLE [4] LC2_CRC_IRQ CRC error for logical channel 2:
LC2_CRC_IRQ This interrupt is triggered on the detection of a
CRC error into the CCP2 data stream.
CCP2_LC23_IRQSTATUS [3] CCP2_LC23_IRQENABLE [3] LC2_FSP_IRQ False synchronization code protection error for
LC2_FSP_IRQ logical channel 2:
This interrupt is triggered by the FSP decoder if an
illegal combination is detected, but 0xA5 is not
present in the bit stream.
CCP2_LC23_IRQSTATUS [2] CCP2_LC23_IRQENABLE [2] LC2_FW_IRQ Frame-width error for logical channel 2:
LC2_FW_IRQ This interrupt is triggered on the detection of a
frame-width error into the CCP2 data stream.
CCP2_LC23_IRQSTATUS [1] CCP2_LC23_IRQENABLE [1] LC2_FSC_IRQ False synchronization code error error for logical
LC2_FSC_IRQ channel 2:
This interrupt is triggered on the detection of a
false synchronization code error into the CCP2
data stream.
CCP2_LC23_IRQSTATUS [0] CCP2_LC23_IRQENABLE [0] LC2_SSC_IRQ Shifted synchronization code error for logical
LC2_SSC_IRQ channel 2:
This interrupt is triggered if LEC or FEC are not
aligned on a 32-bit boundary. This state is shown
in the CCP2 receiver finite state-machine. The
shifted synchronization code error is highlighted in
the CCP2 receiver finite state-machine.
(4)
CCP2_LCM_IRQSTATUS [1] CCP2_LCM_IRQENABLE [1] An OCP error occurred on the master read port.
LCM_OCPERROR LCM_OCPERROR This interrupt is triggered on the detection of an
OCP error on the master read port.
CCP2_LCM_IRQSTATUS [0] CCP2_LCM_IRQENABLE [0] LCM_OEF Memory read channel end of frame:
LCM_EOF This interrupt is triggered when a frame has been
completely read from memory.
(4)
This error can be triggered if the complex I/O cell is used in parallel output mode (CCP_CTRL[2]IO_OUT_SEL=1).
Table 6-18 shows CSI2A and CSI2C receivers event generation through the CSI2 interrupt status and
interrupt enable registers.
Table 6-18. Camera ISP CSI2A and CSI2C Receivers Event Generation
Event Mask Description
CSI2_IRQSTATUS [0] CONTEXT0 CSI2_IRQENABLE [0] CONTEXT0 At least one interrupt event enabled from Context
0 occurred (see
Table 6-20 ).
CSI2_IRQSTATUS [1] CONTEXT1 CSI2_IRQENABLE [1] CONTEXT1 At least one interrupt event enabled from Context
1 occurred (see
Table 6-20 ).
CSI2_IRQSTATUS [2] CONTEXT2 CSI2_IRQENABLE [2] CONTEXT2 At least one interrupt event enabled from Context
1 occurred (see
Table 6-20 ).
CSI2_IRQSTATUS [3] CONTEXT3 CSI2_IRQENABLE [3] CONTEXT3 At least one interrupt event enabled from Context
3 occurred (see
Table 6-20 ).
1151 SWPU177N – December 2009 – Revised November 2010 Camera Image Signal Processor
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