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P3.0/UCB0SIMO/UCB0SDA
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
P3.4/UCA0RXD/UCA0SOMI
P3.5/TB0.5
P3.6/TB0.6
P3.7/TB0OUTH/SVMOUT

Direction
0: Input
1: Output

P3SEL.x

1

0

P3DIR.x

P3IN.x

EN

To module

1

0

From module

P3OUT.x

1

0

DV

SS

DV

CC

P3REN.x

Pad Logic

1

P3DS.x
0: Low drive
1: High drive

D

From module

MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526
MSP430F5525, MSP430F5524, MSP430F5522, MSP430F5521

MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513

www.ti.com

SLAS590M – MARCH 2009 – REVISED NOVEMBER 2015

6.10.3 Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger

Table 6-48. Port P3 (P3.0 to P3.7) Pin Functions

CONTROL BITS OR SIGNALS

(1)

PIN NAME (P3.x)

x

FUNCTION

P3DIR.x

P3SEL.x

P3.0/UCB0SIMO/UCB0SDA

0

P3.0 (I/O)

I: 0; O: 1

0

UCB0SIMO/UCB0SDA

(2) (3)

X

1

P3.1/UCB0SOMI/UCB0SCL

1

P3.1 (I/O)

I: 0; O: 1

0

UCB0SOMI/UCB0SCL

(2) (3)

X

1

P3.2/UCB0CLK/UCA0STE

2

P3.2 (I/O)

I: 0; O: 1

0

UCB0CLK/UCA0STE

(2) (4)

X

1

P3.3/UCA0TXD/UCA0SIMO

3

P3.3 (I/O)

I: 0; O: 1

0

UCA0TXD/UCA0SIMO

(2)

X

1

P3.4/UCA0RXD/UCA0SOMI

4

P3.4 (I/O)

I: 0; O: 1

0

UCA0RXD/UCA0SOMI

(2)

X

1

P3.5/TB0.5

(5)

5

P3.5 (I/O)

I: 0; O: 1

0

TB0.CCI5A

0

1

TB0.5

1

1

P3.6/TB0.6

(5)

6

P3.6 (I/O)

I: 0; O: 1

0

TB0.CCI6A

0

1

TB0.6

1

1

P3.7/TB0OUTH/SVMOUT

(5)

7

P3.7 (I/O)

I: 0; O: 1

0

TB0OUTH

0

1

SVMOUT

1

1

(1)

X = Don't care

(2)

The pin direction is controlled by the USCI module.

(3)

If the I

2

C functionality is selected, the output drives only the logical 0 to V

SS

level.

(4)

UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI A0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.

(5)

F5529, F5527, F5525, F5521, F5519, F5517, F5515 devices only.

Copyright © 2009–2015, Texas Instruments Incorporated

Detailed Description

85

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Product Folder Links:

MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524

MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513

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Summary of Contents for MSP430F5527

Page 1: ...upply Supervisor Operational Full RAM Retention Synchronous SPI Fast Wake up USCI_B0 and USCI_B1 Each Support 1 4 µA at 3 0 V Typical I2 C Off Mode LPM4 Synchronous SPI Full RAM Retention Supply Supervisor Full Speed Universal Serial Bus USB Operational Fast Wake up Integrated USB PHY 1 1 µA at 3 0 V Typical Integrated 3 3 V and 1 8 V USB Power System Shutdown Mode LPM4 5 Integrated USB PLL 0 18 µ...

Page 2: ...524 and MSP430F5522 microcontrollers include all of these peripherals but have 47 I O pins The MSP430F5519 MSP430F5517 and MSP430F5515 microcontrollers have integrated USB and PHY supporting USB 2 0 four 16 bit timers two universal serial communication interfaces USCI a hardware multiplier DMA an RTC module with alarm capabilities and 63 I O pins The MSP430F5514 and MSP430FF5513 microcontrollers i...

Page 3: ...CC Registers TA1 Timer_A 3 CC Registers TB0 Timer_B 7 CC Registers RTC_A CRC16 USCI0 1 USCI_Ax UART IrDA SPI USCI_Bx SPI I2C ADC12_A 200 KSPS 16 Channels 14 ext 2 int Autoscan 12 Bit DVCC DVSS AVCC AVSS P1 x P2 x P3 x P4 x P5 x P6 x DP DM PUR RST NMI TA2 Timer_A 3 CC Registers REF VCORE MAB MDB P7 x P8 x COMP_B 12 Channels MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP...

Page 4: ... Os I O Ports P7 P8 1 8 I Os 1 PD 1 11 I Os 3 I Os Full speed USB USB PHY USB LDO USB PLL MPY32 TA0 Timer_A 5 CC Registers TA1 Timer_A 3 CC Registers TB0 Timer_B 7 CC Registers RTC_A CRC16 USCI0 1 USCI_Ax UART IrDA SPI USCI_Bx SPI I2C DVCC DVSS AVCC AVSS P1 x P2 x P3 x P4 x P5 x P6 x DP DM PUR RST NMI TA2 Timer_A 3 CC Registers COMP_B 12 Channels VCORE MAB MDB P7 x P8 x REF MSP430F5529 MSP430F5528...

Page 5: ... 0 to P4 7 P5 0 to P5 7 P6 0 to P6 7 P7 0 to P7 7 P8 0 to 5 46 USB PWR USB Power System 48 P8 2 PJ 0 to PJ 3 RST NMI 24 5 47 USB PLL USB Phase Locked Loop 48 5 10 Outputs General Purpose I O Full Drive Strength 5 48 Flash Memory 49 P1 0 to P1 7 P2 0 to P2 7 P3 0 to P3 7 P4 0 to P4 7 P5 0 to P5 7 P6 0 to P6 7 P7 0 to P7 7 P8 0 to 5 49 JTAG and Spy Bi Wire Interface 49 P8 2 PJ 0 to PJ 3 24 6 Detaile...

Page 6: ... pF to 1 pF 28 Corrected MRG0 and MRG1 bit names in fMCLK MRG parameter description 49 Corrected spelling of NMIIFG in Table 6 9 System Module Interrupt Vector Registers 60 Corrected register names added USB prefix as necessary in Table 6 45 USB Control Registers 80 Changed P5 3 schematic added P5SEL 2 and XT2BYPASS inputs AND gate and OR gate after P5SEL 3 89 Changed P5SEL 3 column from X to 0 fo...

Page 7: ...urrent part package and ordering information for all available devices see the Package Option Addendum in Section 8 or see the TI website at www ti com 2 Package drawings thermal data and symbolization are available at www ti com packaging 3 The additional 2KB USB SRAM that is listed can be used as general purpose SRAM when USB is not in use 4 Each number in the sequence represents an instantiatio...

Page 8: ...1 P1 4 TA0 3 P2 1 TA1 2 P3 6 TB0 6 P3 7 TB0OUTH SVMOUT P4 2 PM_UCB1SOMI PM_UCB1SCL P4 1 PM_UCB1SIMO PM_UCB1SDA P4 0 PM_UCB1STE PM_UCA1CLK P4 5 PM_UCA1RXD PM_UCA1SOMI P4 4 PM_UCA1TXD PM_UCA1SIMO P4 3 PM_UCB1CLK PM_UCA1STE P4 6 PM_NONE P4 7 PM_NONE P5 6 TB0 0 P5 7 TB0 1 P7 6 TB0 4 P7 7 TB0CLK MCLK P6 3 CB3 A3 P6 2 CB2 A2 P6 1 CB1 A1 P6 0 CB0 A0 P3 5 TB0 5 P8 0 P8 1 P8 2 MSP430F5529 MSP430F5528 MSP43...

Page 9: ...3 16 34 15 35 14 36 13 37 12 38 11 45 4 46 3 47 2 48 1 39 10 40 9 41 8 42 7 43 6 44 5 P1 4 TA 0 3 P1 5 TA 0 4 RST NMI SBWTDIO PJ 3 TCK PJ 2 TMS PJ 1 TDI TCLK PJ 0 TDO TEST SBWTCK P5 3 XT2OUT P5 2 XT2IN AVSS2 V18 VUSB VBUS PU 1 DM PUR PU 0 DP VSSU VCORE MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP...

Page 10: ...0 3 DVSS1 DVCC1 P1 4 TA 0 3 P2 1 TA1 2 P3 6 TB0 6 P3 7 TB0OUTH SVMOUT P4 2 PM_UCB1SOMI PM_UCB1SCL P4 1 PM_UCB1SIMO PM_UCB1SDA P4 0 PM_UCB1STE PM_UCA1CLK P4 5 PM_UCA1RXD PM_UCA1SOMI P4 4 PM_UCA1TXD PM_UCA1SIMO P4 3 PM_UCB1CLK PM_UCA1STE P4 6 PM_NONE P4 7 PM_NONE P5 6 TB0 0 P5 7 TB0 1 P7 6 TB0 4 P7 7 TB0CLK MCLK P6 3 CB3 P6 2 CB2 P6 1 CB1 P6 0 CB0 P3 5 TB0 5 P8 0 P8 1 P8 2 MSP430F5529 MSP430F5528 MS...

Page 11: ... 35 14 36 13 37 12 38 11 45 4 46 3 47 2 48 1 39 10 40 9 41 8 42 7 43 6 44 5 P1 4 TA 0 3 P1 5 TA 0 4 RST NMI SBWTDIO PJ 3 TCK PJ 2 TMS PJ 1 TDI TCLK PJ 0 TDO TEST SBWTCK P5 3 XT2OUT P5 2 XT2IN AVSS2 V18 VUSB VBUS PU 1 DM PUR PU 0 DP VSSU VCORE MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 w...

Page 12: ...7 Reserved Reserved Reserved P1 2 P1 1 Reserved P2 1 Reserved P3 4 MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 SLAS590M MARCH 2009 REVISED NOVEMBER 2015 www ti com Figure 4 5 shows the pinout for the MSP430F5528 MSP430F5526 MSP430F5524 MSP430F5522 MSP430F5514 and MSP430F5513 devices in t...

Page 13: ...S1 P6 0 P6 4 P6 5 P5 0 P5 1 P1 1 P1 0 VCORE PJ 2 PJ 3 P5 3 AVSS2 PJ 1 RST NMI P1 5 P1 6 P1 7 P5 2 V18 P4 7 P2 0 P2 3 P2 2 P2 1 VUSB VBUS P4 3 P4 0 P2 4 PU 1 PUR P4 2 P3 4 P3 0 PU 0 VSSU P4 1 DVCC2 DVSS2 P3 1 P2 7 P6 3 P6 7 P1 2 P1 4 P1 3 PJ 0 TEST P4 6 P4 5 P4 4 P2 6 P3 3 P2 5 P3 2 P6 1 D E D E MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5...

Page 14: ...B10 not available on F5528 F5526 F5524 F5522 F5514 F5513 devices Analog input A14 ADC not available on F551x devices General purpose digital I O not available on F5528 F5526 F5524 F5522 F5514 F5513 devices P7 3 CB11 A15 8 N A N A N A I O Comparator_B input CB11 not available on F5528 F5526 F5524 F5522 F5514 F5513 devices Analog input A15 ADC not available on F551x devices General purpose digital I...

Page 15: ...ture CCI0A input compare Out0 output General purpose digital I O with port interrupt P2 0 TA1 1 29 26 E5 J5 I O TA1 CCR1 capture CCI1A input compare Out1 output General purpose digital I O with port interrupt P2 1 TA1 2 30 27 E8 G6 I O TA1 CCR2 capture CCI2A input compare Out2 output General purpose digital I O with port interrupt P2 2 TA2CLK SMCLK 31 28 E7 J6 I O TA2 clock signal TA2CLK input SMC...

Page 16: ...put USCI_A1 SPI slave mode Default mapping Clock signal output USCI_A1 SPI master mode General purpose digital I O with reconfigurable port mapping secondary function P4 1 PM_UCB1SIMO Default mapping Slave in master out USCI_B1 SPI mode 46 42 H4 E7 I O PM_UCB1SDA Default mapping I2 C data USCI_B1 I2 C mode General purpose digital I O with reconfigurable port mapping secondary function P4 2 PM_UCB1...

Page 17: ...2 P7 7 TB0CLK MCLK 60 N A N A N A I O F5514 F5513 devices MCLK output not available on F5528 F5526 F5524 F5522 F5514 F5513 devices B8 VSSU 61 49 H2 USB PHY ground supply B9 General purpose digital I O Controlled by USB control register PU 0 DP 62 50 H1 A9 I O USB data terminal DP USB pullup resistor pin open drain The voltage level at the PUR pin is used to PUR 63 51 G2 B7 I O invoke the default U...

Page 18: ...input CB1 Analog input A1 ADC not available on F551x devices General purpose digital I O P6 2 CB2 A2 79 3 A1 B1 I O Comparator_B input CB2 Analog input A2 ADC not available on F551x devices General purpose digital I O P6 3 CB3 A3 80 4 C4 C2 I O Comparator_B input CB3 Analog input A3 ADC not available on F551x devices Reserved N A N A N A 6 Reserved Connect to ground QFN Pad N A Pad N A N A QFN pac...

Page 19: ...1000 V may actually have higher performance 2 JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process Pins listed as 250 V may actually have higher performance 5 3 Recommended Operating Conditions Typical values are specified at VCC 3 3 V and TA 25 C unless otherwise noted MIN NOM MAX UNIT PMMCOREVx 0 1 8 3 6 PMMCOREVx 0 1 2 0 3 6 Supply voltage du...

Page 20: ... default condition PMMCOREVx 1 0 12 0 Processor frequency maximum MCLK frequency 5 2 0 V VCC 3 6 V fSYSTEM MHz see Figure 5 1 PMMCOREVx 2 0 20 0 2 2 V VCC 3 6 V PMMCOREVx 3 0 25 0 2 4 V VCC 3 6 V fSYSTEM_USB Minimum processor frequency for USB operation 1 5 MHz USB_wait Wait state cycles during USB operation 16 cycles 5 Modules may have a different maximum input clock specification See the specifi...

Page 21: ... 30 1 0 22 1 35 2 0 2 2 IAM RAM RAM 3 0 V mA 2 0 24 1 50 2 2 3 7 4 2 3 0 26 1 60 2 4 3 9 5 3 6 2 1 All inputs are tied to 0 V or to VCC Outputs do not source or sink any current 2 The currents are characterized with a Micro Crystal MS1V T1K crystal with a load capacitance of 12 5 pF The internal and external load capacitance are chosen to closely match the required 12 5 pF 3 Characterized with pro...

Page 22: ...closely match the required 12 5 pF 3 Current for watchdog timer clocked by SMCLK included ACLK low frequency crystal operation XTS 0 XT1DRIVEx 0 CPUOFF 1 SCG0 0 SCG1 0 OSCOFF 0 LPM0 fACLK 32768 Hz fMCLK 0 MHz fSMCLK fDCO 1 MHz USB disabled VUSBEN 0 SLDOEN 0 4 Current for brownout high side supervisor SVSH normal mode included Low side supervisor and monitor disabled SVSL SVML High side monitor dis...

Page 23: ... ambient thermal resistance still air C W LQFP PN 45 High K board JESD51 7 VQFN RGC 25 BGA ZQE 46 LQFP PN 12 θJC Junction to case thermal resistance VQFN RGC 12 C W BGA ZQE 30 LQFP PN 22 θJB Junction to board thermal resistance VQFN RGC 6 C W BGA ZQE 20 Copyright 2009 2015 Texas Instruments Incorporated Specifications 23 Submit Documentation Feedback Product Folder Links MSP430F5529 MSP430F5528 MS...

Page 24: ...han t int 5 9 Leakage Current General Purpose I O P1 0 to P1 7 P2 0 to P2 7 P3 0 to P3 7 P4 0 to P4 7 P5 0 to P5 7 P6 0 to P6 7 P7 0 to P7 7 P8 0 to P8 2 PJ 0 to PJ 3 RST NMI over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN MAX UNIT Ilkg Px x High impedance leakage current 1 2 1 8 V 3 V 50 50 nA 1 The leakage curr...

Page 25: ...imum total current I OHmax and I OLmax for all outputs combined should not exceed 100 mA to hold the maximum voltage drop specified 5 12 Output Frequency General Purpose I O P1 0 to P1 7 P2 0 to P2 7 P3 0 to P3 7 P4 0 to P4 7 P5 0 to P5 7 P6 0 to P6 7 P7 0 to P7 7 P8 0 to P8 2 PJ 0 to PJ 3 over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER...

Page 26: ...430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 SLAS590M MARCH 2009 REVISED NOVEMBER 2015 www ti com 5 13 Typical Characteristics Outputs Reduced Drive Strength PxDS y 0 over recommended ranges of supply voltage and operating free air temperature unless otherwise noted Figure 5 3 Typical Low Level Output Current vs Low Level Figu...

Page 27: ...8 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 www ti com SLAS590M MARCH 2009 REVISED NOVEMBER 2015 5 14 Typical Characteristics Outputs Full Drive Strength PxDS y 1 over recommended ranges of supply voltage and operating free air temperature unless otherwise noted Figure 5 7 Typical Low Level Output Current vs ...

Page 28: ...T Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins If conformal coating is used ensure that it does not induce capacitive or resistive leakage between the oscillator pins 2 When XT1BYPASS is set XT1 circuits are automatically powered down Input signal is a digital square w...

Page 29: ...effective load capacitance of up to 18 pF can be supported 2 To improve EMI on the XT2 oscillator the following guidelines should be observed Keep the traces between the device and the crystal as short as possible Design a good ground plane around the oscillator pins Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT Avoid running PCB traces underneath or adjace...

Page 30: ...er recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT IREFO REFO oscillator current consumption TA 25 C 1 8 V to 3 6 V 3 µA REFO frequency calibrated Measured at ACLK 1 8 V to 3 6 V 32768 Hz fREFO Full temperature range 1 8 V to 3 6 V 3 5 3 5 REFO absolute tolerance calibrated TA 25 C 3 V 1 5 1 5 dfREFO dT R...

Page 31: ...ORSELx 7 DCOx 0 MODx 0 8 5 19 6 MHz fDCO 7 31 DCO frequency 7 31 1 DCORSELx 7 DCOx 31 MODx 0 60 135 MHz Frequency step between range SDCORSEL SRSEL fDCO DCORSEL 1 DCO fDCO DCORSEL DCO 1 2 2 3 ratio DCORSEL and DCORSEL 1 Frequency step between tap SDCO SDCO fDCO DCORSEL DCO 1 fDCO DCORSEL DCO 1 02 1 12 ratio DCO and DCO 1 Duty cycle Measured at SMCLK 40 50 60 DCO frequency temperature dfDCO dT fDCO...

Page 32: ...ORE0 LPM 1 8 V DVCC 3 6 V 1 44 V PMMCOREV 0 5 22 PMM SVS High Side over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SVSHE 0 DVCC 3 6 V 0 nA I SVSH SVS current consumption SVSHE 1 DVCC 3 6 V SVSHFP 0 200 nA SVSHE 1 DVCC 3 6 V SVSHFP 1 1 5 µA SVSHE 1 SVSHRVL 0 1 57 1 68 1 78 SVSHE 1 SVSHRVL 1 1 79 1 88 1 98...

Page 33: ...MSP430x6xx Family User s Guide SLAU208 on recommended settings and use 5 24 PMM SVS Low Side over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SVSLE 0 PMMCOREV 2 0 nA I SVSL SVSL current consumption SVSLE 1 PMMCOREV 2 SVSLFP 0 200 nA SVSLE 1 PMMCOREV 2 SVSLFP 1 1 5 µA SVSLE 1 dVCORE dt 10 mV µs SVSLFP 1 2 ...

Page 34: ...nts the time from the wake up event to the first active edge of MCLK The wake up time depends on the performance mode of the low side supervisor SVSL and low side monitor SVML In this case the SVSLand SVML are in normal mode low current mode when operating in AM LPM0 and LPM1 Various options are available for SVSLand SVML while operating in LPM2 LPM3 and LPM4 See the Power Management Module and Su...

Page 35: ...less otherwise noted 1 see Figure 5 11 and Figure 5 12 PARAMETER TEST CONDITIONS VCC MIN MAX UNIT SMCLK ACLK fUSCI USCI input clock frequency fSYSTEM MHz Duty cycle 50 10 1 8 V 55 PMMCOREV 0 3 0 V 38 tSU MI SOMI input data setup time ns 2 4 V 30 PMMCOREV 3 3 0 V 25 1 8 V 0 PMMCOREV 0 3 0 V 0 tHD MI SOMI input data hold time ns 2 4 V 0 PMMCOREV 3 3 0 V 0 1 8 V 20 UCLK edge to SIMO valid CL 20 pF PM...

Page 36: ...521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 SLAS590M MARCH 2009 REVISED NOVEMBER 2015 www ti com Figure 5 11 SPI Master Mode CKPH 0 Figure 5 12 SPI Master Mode CKPH 1 36 Specifications Copyright 2009 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F55...

Page 37: ...OREV 0 3 0 V 5 tHD SI SIMO input data hold time ns 2 4 V 5 PMMCOREV 3 3 0 V 5 1 8 V 76 UCLK edge to SOMI valid CL 20 pF PMMCOREV 0 3 0 V 60 tVALID SO SOMI output data valid time 2 ns 2 4 V 44 UCLK edge to SOMI valid CL 20 pF PMMCOREV 3 3 0 V 40 1 8 V 18 CL 20 pF PMMCOREV 0 3 0 V 12 tHD SO SOMI output data hold time 3 ns 2 4 V 10 CL 20 pF PMMCOREV 3 3 0 V 8 1 fUCxCLK 1 2tLO HI with tLO HI max tVALI...

Page 38: ...P430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 SLAS590M MARCH 2009 REVISED NOVEMBER 2015 www ti com Figure 5 13 SPI Slave Mode CKPH 0 Figure 5 14 SPI Slave Mode CKPH 1 38 Specifications Copyright 2009 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP43...

Page 39: ... 10 fSCL SCL clock frequency 2 2 V 3 V 0 400 kHz fSCL 100 kHz 4 0 tHD STA Hold time repeated START 2 2 V 3 V µs fSCL 100 kHz 0 6 fSCL 100 kHz 4 7 tSU STA Setup time for a repeated START 2 2 V 3 V µs fSCL 100 kHz 0 6 tHD DAT Data hold time 2 2 V 3 V 0 ns tSU DAT Data setup time 2 2 V 3 V 250 ns fSCL 100 kHz 4 0 tSU STO Setup time for STOP 2 2 V 3 V µs fSCL 100 kHz 0 6 2 2 V 50 600 Pulse duration of...

Page 40: ...P MAX UNIT For specified performance of ADC12 linearity parameters using an external reference voltage or 0 45 4 8 5 0 AVCC as reference 1 fADC12CLK ADC conversion clock For specified performance of ADC12 linearity 2 2 V 3 V MHz 0 45 2 4 4 0 parameters using the internal reference 2 For specified performance of ADC12 linearity 0 45 2 4 2 7 parameters using the internal reference 3 Internal ADC12 f...

Page 41: ... the Internal Reference Voltage over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS 1 VCC MIN TYP MAX UNIT ADC12SR 0 REFOUT 1 fADC12CLK 4 0 MHz 1 7 Integral linearity EI 2 2 V 3 V LSB error 2 ADC12SR 0 REFOUT 0 fADC12CLK 2 7 MHz 2 5 ADC12SR 0 REFOUT 1 fADC12CLK 4 0 MHz 1 0 2 0 Differential ED ADC12SR 0 REFOUT 1 fADC12CLK 2 7...

Page 42: ...11 is selected 4 Error of conversion result 1 LSB 1 The temperature sensor is provided by the REF module See the REF module parametric IREF regarding the current consumption of the temperature sensor 2 The temperature sensor offset can be significant TI recommends a single point calibration to minimize the offset error of the built in temperature sensor The TLV structure contains calibration value...

Page 43: ...lso the MSP430x5xx and MSP430x6xx Family User s Guide SLAU208 5 41 REF Built In Reference over recommended ranges of supply voltage and operating free air temperature unless otherwise noted 1 PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT REFVSEL 2 for 2 5 V 3 V 2 4625 2 50 2 5375 REFON REFOUT 1 IVREF 0 A Positive built in reference REFVSEL 1 for 2 0 V VREF 3 V 1 9503 1 98 2 0097 V voltage output ...

Page 44: ...FVSEL 0 1 2 REFON 1 REFOUT 0 or 1 AVCC AVCC min to AVCC max TA 25 C Power supply rejection ratio PSRR_AC f 1 kHz ΔVpp 100 mV 6 4 mV V AC REFVSEL 0 1 2 REFON 1 REFOUT 0 or 1 AVCC AVCC min to AVCC max REFVSEL 0 1 2 REFOUT 0 75 REFON 0 1 Settling time of reference tSETTLE µs AVCC AVCC min to AVCC max voltage 7 CVREF CVREF max 75 REFVSEL 0 1 2 REFOUT 1 REFON 0 1 5 Contribution only due to the referenc...

Page 45: ... 0 6 1 0 1 8 CBF 1 CBFDLY 01 Propagation delay with filter tPD filter µs active CBPWRMD 00 CBON 1 1 0 1 8 3 4 CBF 1 CBFDLY 10 CBPWRMD 00 CBON 1 1 8 3 4 6 5 CBF 1 CBFDLY 11 Comparator enable time CBON 0 to CBON 1 tEN_CMP 1 2 µs settling time CBPWRMD 00 01 10 tEN_REF Resistor reference enable time CBON 0 to CBON 1 1 1 5 µs VIN VIN VIN Reference voltage for a given VIN reference into resistor VCB_REF...

Page 46: ...Level Output Voltage V I OL Typical Low Level Output Current mA V 3 0 V T 85 ºC CC A V 1 8 V T 85 ºC CC A V 1 8 V T 25 ºC CC A V 3 0 V T 25 ºC CC A MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 SLAS590M MARCH 2009 REVISED NOVEMBER 2015 www ti com Figure 5 17 Ports PU 0 PU 1 Typical Low Lev...

Page 47: ...CL 50 pF tRISE Rise time 4 20 ns 10 90 Rpu on D Full speed differential CL 50 pF tFALL Fall time 4 20 ns 10 90 Rpu on D 5 45 USB Input Ports DP and DM over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER MIN MAX UNIT V CM Differential input common mode range 0 8 2 5 V Z IN Input impedance 300 kΩ VCRS Crossover voltage 1 3 2 0 V VIL Static SE...

Page 48: ... µF CUSB VUSB terminal recommended capacitance 220 nF C18 V18 terminal recommended capacitance 220 nF Within 2 tENABLE Settling time VUSB and V18 2 ms recommended capacitances RPUR Pullup resistance of PUR terminal 5 70 110 150 Ω 1 This voltage is for internal uses only No external DC loading should be applied 2 This represents additional current that can be supplied to the application from the VU...

Page 49: ...m frequency of MCLK 1 MHz ACLK 32768 Hz SMCLK 1 MHz No peripherals are enabled or active 2 The cumulative program time must not be exceeded when writing to a 128 byte flash block This parameter applies to all programming methods individual word or byte write and block write modes 3 These values are hardwired into the state machine of the flash controller 5 49 JTAG and Spy Bi Wire Interface over re...

Page 50: ...ns in conjunction with seven addressing modes for source operand and four addressing modes for destination operand The CPU is integrated with 16 registers that provide reduced instruction execution time The register to register operation execution time is one cycle of the CPU clock Four of the registers R0 to R3 are dedicated as program counter stack pointer status register and constant generator ...

Page 51: ... is disabled FLL loop control is disabled ACLK and SMCLK remain active MCLK is disabled Low power mode 2 LPM2 CPU is disabled MCLK FLL loop control and DCOCLK are disabled DCO DC generator remains enabled ACLK remains active Low power mode 3 LPM3 CPU is disabled MCLK FLL loop control and DCOCLK are disabled DCO DC generator is disabled ACLK remains active Low power mode 4 LPM4 CPU is disabled ACLK...

Page 52: ...skable 0FFEAh 53 TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4 TA0 Maskable 0FFE8h 52 TA0IFG TA0IV 1 3 USB_UBM USB interrupts USBIV 1 3 Maskable 0FFE6h 51 DMA DMA0IFG DMA1IFG DMA2IFG DMAIV 1 3 Maskable 0FFE4h 50 TA1 TA1CCR0 CCIFG0 3 Maskable 0FFE2h 49 TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2 TA1 Maskable 0FFE0h 48 TA1IFG TA1IV 1 3 I O Port P1 P1IFG 0 to P1IFG 7 P1IV 1 3 Maskable 0FFDEh 47 USCI_A1 Receive or Transmit U...

Page 53: ...B RAM 4 0023FFh 001C00h 0023FFh 001C00h 0023FFh 001C00h 0023FFh 001C00h Info A 128 B 128 B 128 B 128 B 0019FFh 001980h 0019FFh 001980h 0019FFh 001980h 0019FFh 001980h Info B 128 B 128 B 128 B 128 B 00197Fh 001900h 00197Fh 001900h 00197Fh 001900h 00197Fh 001900h Information memory flash Info C 128 B 128 B 128 B 128 B 0018FFh 001880h 0018FFh 001880h 0018FFh 001880h 0018FFh 001880h Info D 128 B 128 B...

Page 54: ...nctions DEVICE SIGNAL BSL FUNCTION PU 0 DP USB data terminal DP PU 1 DM USB data terminal DM PUR USB pullup resistor terminal VBUS USB bus power supply VSSU USB ground supply NOTE The default USB BSL evaluates the logic level of the PUR pin after a BOR reset If the PUR pin is pulled high externally then the BSL is invoked Therefore unless the application is invoking the BSL it is important to keep...

Page 55: ...JTAG state control PJ 1 TDI TCLK IN JTAG data input TCLK input PJ 0 TDO OUT JTAG data output TEST SBWTCK IN Enable JTAG pins RST NMI SBWTDIO IN External reset VCC Power supply VSS Ground supply 6 6 2 Spy Bi Wire Interface In addition to the standard JTAG interface the MSP430 family supports the two wire Spy Bi Wire interface Spy Bi Wire can be used to interface with MSP430 development tools and de...

Page 56: ... that contain USB memory the USB memory can be used as normal RAM if USB is not required 6 9 Peripherals Peripherals are connected to the CPU through data address and control buses Peripherals can be handled using all instructions For complete module descriptions see the MSP430x5xx and MSP430x6xx Family User s Guide SLAU208 6 9 1 Digital I O Link to User s Guide There are up to eight 8 bit I O por...

Page 57: ...ut 11 PM_UCA1SOMI USCI_A1 SPI slave out master in direction controlled by USCI PM_UCA1TXD USCI_A1 UART TXD Direction controlled by USCI output 12 PM_UCA1SIMO USCI_A1 SPI slave in master out direction controlled by USCI PM_UCA1CLK USCI_A1 clock input output direction controlled by USCI 13 PM_UCB1STE USCI_B1 SPI slave transmit enable direction controlled by USCI PM_UCB1SOMI USCI_B1 SPI slave out mas...

Page 58: ... modulator stabilizes the DCO frequency to a programmable multiple of the selected FLL reference frequency The internal DCO provides a fast turnon clock source and stabilizes in 3 5 µs typical The UCS module provides the following clock signals Auxiliary clock ACLK sourced from a 32 kHz watch crystal XT1 a high frequency crystal XT2 the internal low frequency oscillator VLO the trimmed low frequen...

Page 59: ...an generate interrupts at selected time intervals 6 9 8 System Module SYS Link to User s Guide The SYS module handles many of the system functions within the device These include power on reset and power up clear handling NMI source selection and management reset interrupt vector generators bootstrap loader entry mechanisms and configuration management device descriptors It also includes a data ex...

Page 60: ...s system power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a peripheral The USB timestamp generator also uses the DMA trigger assignments described in Table 6 10 Table 6 10 DMA Trigger Assignments 1 CHANNEL TRIGGER 0 1 2 0 DMAREQ DMAREQ DMAREQ 1 TA0CCR0 CCIFG TA0CCR0 CCIFG TA0CCR0 CCIFG 2 TA0CCR2 CCIFG TA0CCR2 CCIFG TA0CCR2 CCIFG 3 TA1CC...

Page 61: ...E0 DMAE0 2 Only on devices with ADC Reserved on devices without ADC 6 9 10 Universal Serial Communication Interface USCI Links to User s Guide UART Mode SPI Mode I2 C Mode The USCI modules are used for serial data communication The USCI module supports synchronous communication protocols such as SPI 3 pin or 4 pin and I2 C and asynchronous communication protocols such as UART enhanced UART with au...

Page 62: ... P1 0 21 P1 0 TA0CLK TACLK ACLK ACLK internal Timer NA NA SMCLK SMCLK internal 18 H2 P1 0 21 P1 0 TA0CLK TACLK 19 H3 P1 1 22 P1 1 TA0 0 CCI0A 19 H3 P1 1 22 P1 1 DVSS CCI0B CCR0 TA0 TA0 0 DVSS GND DVCC VCC 20 J3 P1 2 23 P1 2 TA0 1 CCI1A 20 J3 P1 2 23 P1 2 ADC12 ADC12 CBOUT internal 1 internal 1 CCI1B internal ADC12SHSx ADC12SHSx CCR1 TA1 TA0 1 1 1 DVSS GND DVCC VCC 21 G4 P1 3 24 P1 3 TA0 2 CCI2A 21...

Page 63: ...NUMBER DEVICE MODULE MODULE DEVICE MODULE INPUT INPUT OUTPUT OUTPUT RGC YFF RGC YFF BLOCK PN PN SIGNAL SIGNAL SIGNAL SIGNAL ZQE ZQE 24 G5 P1 6 27 P1 6 TA1CLK TACLK ACLK ACLK internal Timer NA NA SMCLK SMCLK internal 24 G5 P1 6 27 P1 6 TA1CLK TACLK 25 H5 P1 7 28 P1 7 TA1 0 CCI0A 25 H5 P1 7 28 P1 7 DVSS CCI0B CCR0 TA0 TA1 0 DVSS GND DVCC VCC 26 J5 P2 0 29 P2 0 TA1 1 CCI1A 26 J5 P2 0 29 P2 0 CBOUT CC...

Page 64: ...NUMBER DEVICE MODULE MODULE DEVICE MODULE INPUT INPUT OUTPUT OUTPUT RGC YFF RGC YFF BLOCK PN PN SIGNAL SIGNAL SIGNAL SIGNAL ZQE ZQE 28 J6 P2 2 31 P2 2 TA2CLK TACLK ACLK ACLK internal Timer NA NA SMCLK SMCLK internal 28 J6 P2 2 31 P2 2 TA2CLK TACLK 29 H6 P2 3 32 P2 3 TA2 0 CCI0A 29 H6 P2 3 32 P2 3 DVSS CCI0B CCR0 TA0 TA2 0 DVSS GND DVCC VCC 30 J7 P2 4 33 P2 4 TA2 1 CCI1A 30 J7 P2 4 33 P2 4 CBOUT CC...

Page 65: ...K 55 P5 6 TB0 0 CCI0A 55 P5 6 ADC12 ADC12 internal 2 internal 2 55 P5 6 TB0 0 CCI0B ADC12SHSx ADC12SHSx CCR0 TB0 TB0 0 2 2 DVSS GND DVCC VCC 56 P5 7 TB0 1 CCI1A 56 P5 7 ADC12 internal ADC12 internal CBOUT CCI1B ADC12SHSx ADC12SHSx internal CCR1 TB1 TB0 1 3 3 DVSS GND DVCC VCC 57 P7 4 TB0 2 CCI2A 57 P7 4 57 P7 4 TB0 2 CCI2B CCR2 TB2 TB0 2 DVSS GND DVCC VCC 58 P7 5 TB0 3 CCI3A 58 P7 5 58 P7 5 TB0 3 ...

Page 66: ...F is responsible for generation of all critical reference voltages that can be used by the various analog peripherals in the device 6 9 19 Universal Serial Bus USB Link to User s Guide The USB module is a fully integrated USB interface that is compliant with the USB 2 0 specification The module supports full speed operation of control interrupt and bulk transfers The module includes an integrated ...

Page 67: ...27 0220h 000h 00Bh Port P5 and P6 see Table 6 28 0240h 000h 00Bh Port P7 and P8 see Table 6 29 0260h 000h 00Bh Port PJ see Table 6 30 0320h 000h 01Fh TA0 see Table 6 31 0340h 000h 02Eh TA1 see Table 6 32 0380h 000h 02Eh TB0 see Table 6 33 03C0h 000h 02Eh TA2 see Table 6 34 0400h 000h 02Eh Real Time Clock RTC_A see Table 6 35 04A0h 000h 01Bh 32 Bit Hardware Multiplier see Table 6 36 04C0h 000h 02Fh...

Page 68: ...ontrol 4 FCTL4 06h Table 6 19 CRC16 Registers Base Address 0150h REGISTER DESCRIPTION REGISTER OFFSET CRC data input CRC16DI 00h CRC data input reverse byte CRCDIRB 02h CRC initialization and result CRCINIRES 04h CRC result reverse byte CRCRESR 06h Table 6 20 RAM Control Registers Base Address 0158h REGISTER DESCRIPTION REGISTER OFFSET RAM control 0 RCCTL0 00h Table 6 21 Watchdog Registers Base Ad...

Page 69: ...h Reset vector generator SYSRSTIV 1Eh Table 6 24 Shared Reference Registers Base Address 01B0h REGISTER DESCRIPTION REGISTER OFFSET Shared reference control REFCTL 00h Table 6 25 Port Mapping Registers Base Address of Port Mapping Control 01C0h Port P4 01E0h REGISTER DESCRIPTION REGISTER OFFSET Port mapping key and ID register PMAPKEYID 00h Port mapping control register PMAPCTL 02h Port P4 0 mappi...

Page 70: ... 07h Port P2 drive strength P2DS 09h Port P2 selection P2SEL 0Bh Port P2 interrupt vector word P2IV 1Eh Port P2 interrupt edge select P2IES 19h Port P2 interrupt enable P2IE 1Bh Port P2 interrupt flag P2IFG 1Dh Table 6 27 Port P3 and P4 Registers Base Address 0220h REGISTER DESCRIPTION REGISTER OFFSET Port P3 input P3IN 00h Port P3 output P3OUT 02h Port P3 direction P3DIR 04h Port P3 pullup or pul...

Page 71: ...h REGISTER DESCRIPTION REGISTER OFFSET Port P7 input P7IN 00h Port P7 output P7OUT 02h Port P7 direction P7DIR 04h Port P7 pullup or pulldown enable P7REN 06h Port P7 drive strength P7DS 08h Port P7 selection P7SEL 0Ah Port P8 input P8IN 01h Port P8 output P8OUT 03h Port P8 direction P8DIR 05h Port P8 pullup or pulldown enable P8REN 07h Port P8 drive strength P8DS 09h Port P8 selection P8SEL 0Bh T...

Page 72: ...pture compare register 3 TA0CCR3 18h Capture compare register 4 TA0CCR4 1Ah TA0 expansion register 0 TA0EX0 20h TA0 interrupt vector TA0IV 2Eh Table 6 32 TA1 Registers Base Address 0380h REGISTER DESCRIPTION REGISTER OFFSET TA1 control TA1CTL 00h Capture compare control 0 TA1CCTL0 02h Capture compare control 1 TA1CCTL1 04h Capture compare control 2 TA1CCTL2 06h TA1 counter register TA1R 10h Captur...

Page 73: ...e compare register 3 TB0CCR3 18h Capture compare register 4 TB0CCR4 1Ah Capture compare register 5 TB0CCR5 1Ch Capture compare register 6 TB0CCR6 1Eh TB0 expansion register 0 TB0EX0 20h TB0 interrupt vector TB0IV 2Eh Table 6 34 TA2 Registers Base Address 0400h REGISTER DESCRIPTION REGISTER OFFSET TA2 control TA2CTL 00h Capture compare control 0 TA2CCTL0 02h Capture compare control 1 TA2CCTL1 04h C...

Page 74: ...interrupt vector word RTCIV 0Eh RTC seconds RTC counter register 1 RTCSEC RTCNT1 10h RTC minutes RTC counter register 2 RTCMIN RTCNT2 11h RTC hours RTC counter register 3 RTCHOUR RTCNT3 12h RTC day of week RTC counter register 4 RTCDOW RTCNT4 13h RTC days RTCDAY 14h RTC month RTCMON 15h RTC year low RTCYEARL 16h RTC year high RTCYEARH 17h RTC alarm minutes RTCAMIN 18h RTC alarm hours RTCAHOUR 19h ...

Page 75: ... MPY32H 12h 32 bit operand 1 signed multiply low word MPYS32L 14h 32 bit operand 1 signed multiply high word MPYS32H 16h 32 bit operand 1 multiply accumulate low word MAC32L 18h 32 bit operand 1 multiply accumulate high word MAC32H 1Ah 32 bit operand 1 signed multiply accumulate low word MACS32L 1Ch 32 bit operand 1 signed multiply accumulate high word MACS32H 1Eh 32 bit operand 2 low word OP2L 20...

Page 76: ...ource address high DMA2SAH 04h DMA channel 2 destination address low DMA2DAL 06h DMA channel 2 destination address high DMA2DAH 08h DMA channel 2 transfer size DMA2SZ 0Ah DMA module control 0 DMACTL0 00h DMA module control 1 DMACTL1 02h DMA module control 2 DMACTL2 04h DMA module control 3 DMACTL3 06h DMA module control 4 DMACTL4 08h DMA interrupt vector DMAIV 0Eh Table 6 38 USCI_A0 Registers Base...

Page 77: ...interrupt flags UCB0IFG 1Dh USCI interrupt vector word UCB0IV 1Eh Table 6 40 USCI_A1 Registers Base Address 0600h REGISTER DESCRIPTION REGISTER OFFSET USCI control 1 UCA1CTL1 00h USCI control 0 UCA1CTL0 01h USCI baud rate 0 UCA1BR0 06h USCI baud rate 1 UCA1BR1 07h USCI modulation control UCA1MCTL 08h USCI status UCA1STAT 0Ah USCI receive buffer UCA1RXBUF 0Ch USCI transmit buffer UCA1TXBUF 0Eh USCI...

Page 78: ...ynchronous bit rate 1 UCB1BR1 07h USCI synchronous status UCB1STAT 0Ah USCI synchronous receive buffer UCB1RXBUF 0Ch USCI synchronous transmit buffer UCB1TXBUF 0Eh USCI I2C own address UCB1I2COA 10h USCI I2C slave address UCB1I2CSA 12h USCI interrupt enable UCB1IE 1Ch USCI interrupt flags UCB1IFG 1Dh USCI interrupt vector word UCB1IV 1Eh 78 Detailed Description Copyright 2009 2015 Texas Instrument...

Page 79: ...ster 9 ADC12MCTL9 19h ADC memory control register 10 ADC12MCTL10 1Ah ADC memory control register 11 ADC12MCTL11 1Bh ADC memory control register 12 ADC12MCTL12 1Ch ADC memory control register 13 ADC12MCTL13 1Dh ADC memory control register 14 ADC12MCTL14 1Eh ADC memory control register 15 ADC12MCTL15 1Fh Conversion memory 0 ADC12MEM0 20h Conversion memory 1 ADC12MEM1 22h Conversion memory 2 ADC12MEM...

Page 80: ...2h USB PLL interrupts USBPLLIR 14h Table 6 45 USB Control Registers Base Address 0920h REGISTER DESCRIPTION REGISTER OFFSET Input endpoint_0 configuration USBIEPCNF_0 00h Input endpoint_0 byte count USBIEPCNT_0 01h Output endpoint_0 configuration USBOEPCNF_0 02h Output endpoint_0 byte count USBOEPCNT_0 03h Input endpoint interrupt enables USBIEPIE 0Eh Output endpoint interrupt enables USBOEPIE 0Fh...

Page 81: ...5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 www ti com SLAS590M MARCH 2009 REVISED NOVEMBER 2015 6 10 Input Output Schematics 6 10 1 Port P1 P1 0 to P1 7 Input Output With Schmitt Trigger Copyright 2009 2015 Texas Instruments Incorporated Detailed Description 81 Submit Documentation Feedback Product Folder...

Page 82: ... P1 2 TA0 1 2 P1 2 I O I 0 O 1 0 TA0 CCI1A 0 1 TA0 1 1 1 P1 3 TA0 2 3 P1 3 I O I 0 O 1 0 TA0 CCI2A 0 1 TA0 2 1 1 P1 4 TA0 3 4 P1 4 I O I 0 O 1 0 TA0 CCI3A 0 1 TA0 3 1 1 P1 5 TA0 4 5 P1 5 I O I 0 O 1 0 TA0 CCI4A 0 1 TA0 4 1 1 P1 6 TA1CLK CBOUT 6 P1 6 I O I 0 O 1 0 TA1CLK 0 1 CBOUT comparator B 1 1 P1 7 TA1 0 7 P1 7 I O I 0 O 1 0 TA1 CCI0A 0 1 TA1 0 1 1 82 Detailed Description Copyright 2009 2015 Te...

Page 83: ...e MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 www ti com SLAS590M MARCH 2009 REVISED NOVEMBER 2015 6 10 2 Port P2 P2 0 to P2 7 Input Output With Schmitt Trigger Copyright 2009 2015 Texas Instruments Incorporated Detailed Description 83 Submit Documentation Feedback Product Folder Links M...

Page 84: ...A2 1 4 P2 4 I O I 0 O 1 0 TA2 CCI1A 0 1 TA2 1 1 1 P2 5 TA2 2 5 P2 5 I O I 0 O 1 0 TA2 CCI2A 0 1 TA2 2 1 1 P2 6 RTCCLK DMAE0 6 P2 6 I O I 0 O 1 0 DMAE0 0 1 RTCCLK 1 1 P2 7 UCB0STE UCA0CLK 7 P2 7 I O I 0 O 1 0 UCB0STE UCA0CLK 2 3 X 1 1 X Don t care 2 The pin direction is controlled by the USCI module 3 UCA0CLK function takes precedence over UCB0STE function If the pin is required as UCA0CLK input or...

Page 85: ... UCB0CLK UCA0STE 2 P3 2 I O I 0 O 1 0 UCB0CLK UCA0STE 2 4 X 1 P3 3 UCA0TXD UCA0SIMO 3 P3 3 I O I 0 O 1 0 UCA0TXD UCA0SIMO 2 X 1 P3 4 UCA0RXD UCA0SOMI 4 P3 4 I O I 0 O 1 0 UCA0RXD UCA0SOMI 2 X 1 P3 5 TB0 5 5 5 P3 5 I O I 0 O 1 0 TB0 CCI5A 0 1 TB0 5 1 1 P3 6 TB0 6 5 6 P3 6 I O I 0 O 1 0 TB0 CCI6A 0 1 TB0 6 1 1 P3 7 TB0OUTH SVMOUT 5 7 P3 7 I O I 0 O 1 0 TB0OUTH 0 1 SVMOUT 1 1 1 X Don t care 2 The pin...

Page 86: ...4MAP1 1 P4 1 I O I 0 O 1 0 X Mapped secondary digital function X 1 30 P4 2 P4MAP2 2 P4 2 I O I 0 O 1 0 X Mapped secondary digital function X 1 30 P4 3 P4MAP3 3 P4 3 I O I 0 O 1 0 X Mapped secondary digital function X 1 30 P4 4 P4MAP4 4 P4 4 I O I 0 O 1 0 X Mapped secondary digital function X 1 30 P4 5 P4MAP5 5 P4 5 I O I 0 O 1 0 X Mapped secondary digital function X 1 30 P4 6 P4MAP6 6 P4 6 I O I 0...

Page 87: ...nce for the ADC12_A when available Channel A8 when selected with the INCHx bits is connected to the VREF VeREF pin 5 Setting the P5SEL 0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals The VREF reference is available at the pin Channel A8 when selected with the INCHx bits is connected to the VREF VeREF pin 6 VREF VeREF a...

Page 88: ...0F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 SLAS590M MARCH 2009 REVISED NOVEMBER 2015 www ti com 6 10 6 Port P5 P5 2 Input Output With Schmitt Trigger 88 Detailed Description Copyright 2009 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP4...

Page 89: ...PASS P5 2 XT2IN 2 P5 2 I O I 0 O 1 0 X X XT2IN crystal mode 2 X 1 X 0 XT2IN bypass mode 2 X 1 X 1 P5 3 XT2OUT 3 P5 3 I O I 0 O 1 0 0 X XT2OUT crystal mode 3 X 1 X 0 P5 3 I O 3 X 1 0 1 1 X Don t care 2 Setting P5SEL 2 causes the general purpose I O to be disabled Pending the setting of XT2BYPASS P5 2 is configured for crystal mode or bypass mode 3 Setting P5SEL 2 causes the general purpose I O to b...

Page 90: ...MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 SLAS590M MARCH 2009 REVISED NOVEMBER 2015 www ti com 6 10 7 1 Port P5 P5 4 and P5 5 Input Output With Schmitt Trigger 90 Detailed Description Copyright 2009 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 ...

Page 91: ...I O I 0 O 1 0 X X XIN crystal mode 2 X 1 X 0 XIN bypass mode 2 X 1 X 1 P5 5 XOUT 5 P5 5 I O I 0 O 1 0 0 X XOUT crystal mode 3 X 1 X 0 P5 5 I O 3 X 1 0 1 1 X Don t care 2 Setting P5SEL 4 causes the general purpose I O to be disabled Pending the setting of XT1BYPASS P5 4 is configured for crystal mode or bypass mode 3 Setting P5SEL 4 causes the general purpose I O to be disabled in crystal mode When...

Page 92: ...ort P5 P5 6 to P5 7 Input Output With Schmitt Trigger Table 6 53 Port P5 P5 6 to P5 7 Pin Functions CONTROL BITS OR SIGNALS PIN NAME P5 x x FUNCTION P5DIR x P5SEL x P5 6 TB0 0 1 6 P5 6 I O I 0 O 1 0 TB0 CCI0A 0 1 TB0 0 1 1 P5 7 TB0 1 1 7 TB0 CCI1A 0 1 TB0 1 1 1 1 F5529 F5527 F5525 F5521 F5519 F5517 F5515 devices only 92 Detailed Description Copyright 2009 2015 Texas Instruments Incorporated Submit...

Page 93: ...51x MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 www ti com SLAS590M MARCH 2009 REVISED NOVEMBER 2015 6 10 9 Port P6 P6 0 to P6 7 Input Output With Schmitt Trigger Copyright 2009 2015 Texas Instruments Incorporated Detailed Description 93 Submit Documentation Feedback Product Folder Links...

Page 94: ...F552x X 1 X CB4 1 X X 1 P6 5 CB5 A5 5 P6 5 I O I 0 O 1 0 0 A5 only MSP430F552x X 1 X CB5 1 X X 1 P6 6 CB6 A6 6 P6 6 I O I 0 O 1 0 0 A6 only MSP430F552x X 1 X CB6 1 X X 1 P6 7 CB7 A7 7 P6 7 I O I 0 O 1 0 0 A7 only MSP430F552x X 1 X CB7 1 X X 1 1 Setting the CBPD x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals Selecting ...

Page 95: ...F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 www ti com SLAS590M MARCH 2009 REVISED NOVEMBER 2015 6 10 10 Port P7 P7 0 to P7 3 Input Output With Schmitt Trigger Copyright 2009 2015 Texas Instruments Incorporated Detailed Description 95 Submit Documentation Feedback Product Folder Links MSP430F5529 MSP430F5...

Page 96: ...1 0 0 A15 2 X 1 X CB11 3 1 X X 1 1 F5529 F5527 F5525 F5521 F5519 F5517 F5515 devices only 2 F5529 F5527 F5525 F5521 devices only 3 Setting the CBPD x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input b...

Page 97: ...Table 6 56 Port P7 P7 4 to P7 7 Pin Functions CONTROL BITS OR SIGNALS PIN NAME P7 x x FUNCTION P7DIR x P7SEL x P7 4 TB0 2 1 4 P7 4 I O I 0 O 1 0 TB0 CCI2A 0 1 TB0 2 1 1 P7 5 TB0 3 1 5 P7 5 I O I 0 O 1 0 TB0 CCI3A 0 1 TB0 3 1 1 P7 6 TB0 4 1 6 P7 6 I O I 0 O 1 0 TB0 CCI4A 0 1 TB0 4 1 1 P7 7 TB0CLK MCLK 1 7 P7 7 I O I 0 O 1 0 TB0CLK 0 1 MCLK 1 1 1 F5529 F5527 F5525 F5521 F5519 F5517 F5515 devices onl...

Page 98: ...MBER 2015 www ti com 6 10 12 Port P8 P8 0 to P8 2 Input Output With Schmitt Trigger Table 6 57 Port P8 P8 0 to P8 2 Pin Functions CONTROL BITS OR SIGNALS PIN NAME P8 x x FUNCTION P8DIR x P8SEL x P8 0 1 0 P8 0 I O I 0 O 1 0 P8 1 1 1 P8 1 I O I 0 O 1 0 P8 2 1 2 P8 2 I O I 0 O 1 0 1 F5529 F5527 F5525 F5521 F5519 F5517 F5515 devices only 98 Detailed Description Copyright 2009 2015 Texas Instruments In...

Page 99: ...P430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 www ti com SLAS590M MARCH 2009 REVISED NOVEMBER 2015 6 10 13 Port PU 0 DP PU 1 DM PUR USB Ports Copyright 2009 2015 Texas Instruments Incorporated Detailed Description 99 Submit Documentation Feedback Product Folder Links MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 ...

Page 100: ...utput state set by the USB module Table 6 59 Port PU 0 DP PU 1 DM Input Functions 1 CONTROL BITS PIN NAME PUSEL PUIPE PU 1 DM PU 0 DP 0 0 Input disabled Input disabled 0 1 Input enabled Input enabled 1 X DM input DP input 1 PU 1 DM and PU 0 DP inputs and outputs are supplied from VUSB VUSB can be generated by the device using the integrated 3 3 V LDO when enabled VUSB can also be supplied external...

Page 101: ...522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 www ti com SLAS590M MARCH 2009 REVISED NOVEMBER 2015 6 10 14 Port J J 0 JTAG Pin TDO Input Output With Schmitt Trigger or Output 6 10 15 Port J J 1 to J 3 JTAG Pins TMS TCK TDI TCLK Input Output With Schmitt Trigger or Output Copyright 2009 2015 Texas Instruments Incorporated Detailed Description 101 Submit Documentation F...

Page 102: ... 2 I 0 O 1 TDI TCLK 3 4 X PJ 2 TMS 2 PJ 2 I O 2 I 0 O 1 TMS 3 4 X PJ 3 TCK 3 PJ 3 I O 2 I 0 O 1 TCK 3 4 X 1 X Don t care 2 Default condition 3 The pin direction is controlled by the JTAG module 4 In JTAG mode pullups are activated automatically on TMS TCK and TDI TCLK PJREN x are do not care 102 Detailed Description Copyright 2009 2015 Texas Instruments Incorporated Submit Documentation Feedback P...

Page 103: ...er unit ADC 1 5 V Reference 01A1Ah 2 per unit per unit per unit per unit per unit per unit per unit per unit Temp Sensor 30 C ADC 1 5 V Reference 01A1Ch 2 per unit per unit per unit per unit per unit per unit per unit per unit Temp Sensor 85 C ADC 2 0 V Reference 01A1Eh 2 per unit per unit per unit per unit per unit per unit per unit per unit Temp Sensor 30 C ADC 2 0 V Reference 01A20h 2 per unit ...

Page 104: ...4h 00h 00h 00h 00h 00h 00h 00h 00h WDT_A 2 40h 40h 40h 40h 40h 40h 40h 40h 01h 01h 01h 01h 01h 01h 01h 01h UCS 2 48h 48h 48h 48h 48h 48h 48h 48h 02h 02h 02h 02h 02h 02h 02h 02h SYS 2 42h 42h 42h 42h 42h 42h 42h 42h 03h 03h 03h 03h 03h 03h 03h 03h REF 2 A0h A0h A0h A0h A0h A0h A0h A0h 01h 01h 01h 01h 01h 01h 01h 01h Port Mapping 2 10h 10h 10h 10h 10h 10h 10h 10h 04h 04h 04h 04h 04h 04h 04h 04h Port...

Page 105: ... 93h 93h 93h TA1 CCIFG0 1 66h 66h 66h 66h 66h 66h 66h 66h TA1 CCIFG1 2 1 67h 67h 67h 67h 67h 67h 67h 67h P2 1 51h 51h 51h 51h 51h 51h 51h 51h RTC_A 1 68h 68h 68h 68h 68h 68h 68h 68h delimiter 1 00h 00h 00h 00h 00h 00h 00h 00h Table 6 63 MSP430F551x Device Descriptor Table 1 VALUE SIZE DESCRIPTION ADDRESS bytes F5519 F5517 F5515 F5514 F5513 Info Block Info length 01A00h 1 55h 55h 55h 55h 55h CRC le...

Page 106: ...t per unit per unit per unit per unit Factor Peripheral Peripheral Descriptor Tag 01A2Eh 1 02h 02h 02h 02h 02h Descriptor Peripheral Descriptor 01A2Fh 1 61h 63h 61h 5Fh 5Fh Length 08h 08h 08h 08h 08h Memory 1 2 8Ah 8Ah 8Ah 8Ah 8Ah 0Ch 0Ch 0Ch 0Ch 0Ch Memory 2 2 86h 86h 86h 86h 86h 0Eh 0Eh 0Eh 0Eh 0Eh Memory 3 2 2Ah 2Ah 2Ah 2Ah 2Ah 12h 12h 12h 12h 12h Memory 4 2 2Eh 2Dh 2Ch 2Ch 2Ch 22h 2Ah 22h 22h ...

Page 107: ...7h 67h 67h 04h 04h 04h 04h 04h TA2 2 61h 61h 61h 61h 61h 0Ah 0Ah 0Ah 0Ah 0Ah RTC 2 68h 68h 68h 68h 68h 02h 02h 02h 02h 02h MPY32 2 85h 85h 85h 85h 85h 04h 04h 04h 04h 04h DMA 3 2 47h 47h 47h 47h 47h 0Ch 0Ch 0Ch 0Ch 0Ch USCI_A B 2 90h 90h 90h 90h 90h 04h 04h 04h 04h 04h USCI_A B 2 90h 90h 90h 90h 90h ADC12_A 2 N A N A N A N A N A 2Ch 2Ch 2Ch 2Ch 2Ch COMP_B 2 A8h A8h A8h A8h A8h 04h 04h 04h 04h 04h ...

Page 108: ...17 F5515 F5514 F5513 USCI_A1 1 92h 92h 92h 92h 92h USCI_B1 1 93h 93h 93h 93h 93h TA1 CCIFG0 1 66h 66h 66h 66h 66h TA1 CCIFG1 2 1 67h 67h 67h 67h 67h P2 1 51h 51h 51h 51h 51h RTC_A 1 68h 68h 68h 68h 68h delimiter 1 00h 00h 00h 00h 00h 108 Detailed Description Copyright 2009 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links MSP430F5529 MSP430F5528 MSP430F5527 MSP...

Page 109: ...ping Target socket boards are orderable individually or as a kit with the JTAG programmer and debugger included The following table shows the compatible target boards and the supported packages PACKAGE TARGET BOARD AND PROGRAMMER BUNDLE TARGET BOARD ONLY 64 pin VQFN RGC MSP FET430U64USB MSP TS430RGC64USB 80 pin LQFP PN MSP FET430U80USB MSP TS430PN80USB 7 1 2 2 2 Experimenter Boards Experimenter Bo...

Page 110: ... Flasher can be used to download binary files txt or hex files directly to the MSP430 Flash without the need for an IDE 7 1 3 Device and Development Tool Nomenclature To designate the stages in the product development cycle TI assigns prefixes to the part numbers of all MSP430 MCU devices and support tools Each MSP430 MCU commercial family member has one of three prefixes MSP PMS or XMS for exampl...

Page 111: ...Optional A Revision Optional Tape and Reel Feature Set Optional Additional Features MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 www ti com SLAS590M MARCH 2009 REVISED NOVEMBER 2015 MSP devices and MSP development support tools have been characterized fully and the quality and reliability...

Page 112: ...Z309 MSP430F5524 Device Erratasheet Describes the known exceptions to the functional specifications for all silicon revisions of the device SLAZ308 MSP430F5522 Device Erratasheet Describes the known exceptions to the functional specifications for all silicon revisions of the device SLAZ307 MSP430F5521 Device Erratasheet Describes the known exceptions to the functional specifications for all silico...

Page 113: ... contents are provided AS IS by the respective contributors They do not constitute TI specifications and do not necessarily reflect TI s views see TI s Terms of Use TI E2E Community TI s Engineer to Engineer E2E Community Created to foster collaboration among engineers At e2e ti com you can ask questions share knowledge explore ideas and help solve problems with fellow engineers TI Embedded Proces...

Page 114: ... information is the most current data available for the designated devices This data is subject to change without notice and revision of this document For browser based versions of this data sheet refer to the left hand navigation 114 Mechanical Packaging and Orderable Information Copyright 2009 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links MSP430F5529 MSP4...

Page 115: ...GA MICROSTAR JUNIOR ZQE 80 360 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 40 to 85 M430F5514 MSP430F5514IZQER ACTIVE BGA MICROSTAR JUNIOR ZQE 80 2500 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 40 to 85 M430F5514 MSP430F5515IPN ACTIVE LQFP PN 80 119 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 85 M430F5515 MSP430F5515IPNR ACTIVE LQFP PN 80 1000 Green RoHS no Sb Br CU NIPDAU Level...

Page 116: ...b Br CU NIPDAU CU NIPDAUAG Level 3 260C 168 HR 40 to 85 M430F5524 MSP430F5524IYFFR ACTIVE DSBGA YFF 64 2500 Green RoHS no Sb Br SNAGCU Level 1 260C UNLIM M430F5524 MSP430F5524IZQE ACTIVE BGA MICROSTAR JUNIOR ZQE 80 360 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 40 to 85 M430F5524 MSP430F5524IZQER ACTIVE BGA MICROSTAR JUNIOR ZQE 80 2500 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 40 to 85 M4...

Page 117: ...en RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 85 M430F5529 1 The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this pa...

Page 118: ... finish options Finish options are separated by a vertical ruled line Lead Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes...

Page 119: ... 3 1 5 8 0 12 0 Q1 MSP430F5515IPNR LQFP PN 80 1000 330 0 24 4 15 0 15 0 2 1 20 0 24 0 Q2 MSP430F5517IPNR LQFP PN 80 1000 330 0 24 4 15 0 15 0 2 1 20 0 24 0 Q2 MSP430F5519IPNR LQFP PN 80 1000 330 0 24 4 15 0 15 0 2 1 20 0 24 0 Q2 MSP430F5521IPNR LQFP PN 80 1000 330 0 24 4 15 0 15 0 2 1 20 0 24 0 Q2 MSP430F5522IRGCT VQFN RGC 64 250 180 0 16 4 9 3 9 3 1 5 12 0 16 0 Q2 MSP430F5522IZQER BGA MI CROSTA R...

Page 120: ...F5526IYFFR DSBGA YFF 64 2500 330 0 12 4 3 86 3 86 0 69 8 0 12 0 Q2 MSP430F5526IZQER BGA MI CROSTA R JUNI OR ZQE 80 2500 330 0 12 4 5 3 5 3 1 5 8 0 12 0 Q1 MSP430F5527IPNR LQFP PN 80 1000 330 0 24 4 15 0 15 0 2 1 20 0 24 0 Q2 MSP430F5528IRGCT VQFN RGC 64 250 180 0 16 4 9 3 9 3 1 5 12 0 16 0 Q2 MSP430F5528IYFFR DSBGA YFF 64 2500 330 0 12 4 3 86 3 86 0 69 8 0 12 0 Q2 MSP430F5528IZQER BGA MI CROSTA R ...

Page 121: ...2500 336 6 336 6 28 6 MSP430F5524IRGCT VQFN RGC 64 250 210 0 185 0 35 0 MSP430F5524IYFFR DSBGA YFF 64 2500 367 0 367 0 35 0 MSP430F5524IZQER BGA MICROSTAR JUNIOR ZQE 80 2500 336 6 336 6 28 6 MSP430F5525IPNR LQFP PN 80 1000 367 0 367 0 45 0 MSP430F5526IRGCR VQFN RGC 64 2000 367 0 367 0 38 0 MSP430F5526IRGCT VQFN RGC 64 250 210 0 185 0 35 0 MSP430F5526IYFFR DSBGA YFF 64 2500 367 0 367 0 35 0 MSP430F...

Page 122: ...QUAD FLATPACK 4040135 B 11 96 0 17 0 27 0 13 NOM 40 21 0 25 0 45 0 75 0 05 MIN Seating Plane Gage Plane 41 60 61 80 20 SQ SQ 1 13 80 14 20 12 20 9 50 TYP 11 80 1 45 1 35 1 60 MAX 0 08 0 50 M 0 08 0 7 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MS 026 ...

Page 123: ...D Max E Max 3 79 mm Min 3 79 mm Min 3 73 mm 3 73 mm ...

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Page 128: ... TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN including but not limited to any patent right copyright mask work right or other intellectual property right relating to any combination machine or process in which TI product...

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