MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526
MSP430F5525, MSP430F5524, MSP430F5522, MSP430F5521
MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
SLAS590M – MARCH 2009 – REVISED NOVEMBER 2015
www.ti.com
6.7
Flash Memory
(Link to User's Guide)
The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system
by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory.
Features of the flash memory include:
•
Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
•
Segments 0 to n may be erased in one step, or each segment may be individually erased.
•
Segments A to D can be erased individually. Segments A to D are also called
information memory
.
•
Segment A can be locked separately.
6.8
RAM
(Link to User's Guide)
The RAM is made up of n sectors. Each sector can be completely powered down to save leakage;
however; all data is lost. Features of the RAM include:
•
RAM has n sectors. The size of a sector can be found in
Section 6.4
.
•
Each sector 0 to n can be complete disabled; however, data retention is lost.
•
Each sector 0 to n automatically enters low-power retention mode when possible.
•
For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not
required.
6.9
Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
handled using all instructions. For complete module descriptions, see the
MSP430x5xx and MSP430x6xx
Family User's Guide
(
SLAU208
).
6.9.1
Digital I/O
(Link to User's Guide)
There are up to eight 8-bit I/O ports implemented: For 80 pin options, P1, P2, P3, P4, P5, P6, and P7 are
complete, and P8 is reduced to 3-bit I/O. For 64 pin options, P3 and P5 are reduced to 5-bit I/O and 6-bit
I/O, respectively, and P7 and P8 are completely removed. Port PJ contains four individual I/O ports,
common to all devices.
•
All individual I/O bits are independently programmable.
•
Any combination of input, output, and interrupt conditions is possible.
•
Pullup or pulldown on all ports is programmable.
•
Drive strength on all ports is programmable.
•
Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1 and
P2.
•
Read and write access to port-control registers is supported by all instructions.
•
Ports can be accessed byte-wise (P1 through P8) or word-wise in pairs (PA through PD).
56
Detailed Description
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MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524
MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513
Summary of Contents for MSP430F5527
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