Texas Instruments MSP430F42 series, Instruction Manual

Page: 21 / 42

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
21
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DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f = 1 MHz 6
t
d(LPM3)
Delay time
f = 2 MHz
V
CC
= 3 V
6
μ
s t
d(LPM3)
Delay time
f = 3 MHz
V
CC
3 V
6
μ
s
RAM (see Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRAMh CPU halted (see Note 1) 1.6 V
NOTE 1: This parameter defines the minimum supply voltage when the data in the program memory RAM remain unchanged. No program
execution should take place during this supply voltage condition.
LCD
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(33)
Voltage at R33 2.5 V
CC
+0.2
V
(23)
Analog voltage
Voltage at R23
V 3 V
(V
33
−V
03
)
×
2/3 + V
03
V
V
(13)
Analog voltage
Voltage at R13
V
CC
= 3 V
(V
(33)
−V
(03)
)
×
1/3 + V
(03)
V
V
(33) −
V
(03)
Voltage at R33/R03 2.5 V
CC
+0.2
I
(R03)
R03 = V
SS
No load at all
±
20
I
(R13)
Input leakage R13 = V
CC
/3
segment and
common lines
±
20 nA
I
(R23)
p g
R23 = 2
×
V
CC
/3
common lines,
V
CC
= 3 V
±
20
V
(Sxx0)
V
(03)
V
(03)
− 0.1
V
(Sxx1)
Segment line
I 3 A V 3 V
V
(13)
V
(13)
− 0.1
V
V
(Sxx2)
Segment line
voltage
I
(Sxx)
= −3
μ
A, V
CC
= 3 V
V(
23)
V
(23)
− 0.1
V
V
(Sxx3)
V(
33)
V
(33)
+ 0.1
USART0 (see Note 1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
t
(
τ
)
USART0: deglitch time V
CC
= 3 V, SYNC = 0, UART mode 150 280 500 ns
NOTE 1: The signal applied to the USART0 receive signal/terminal (URXD0) should meet the timing requirements of t
(τ
)
to ensure that the URXS
flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t
(τ
)
. The operating conditions to
set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the
URXD0 line.
POR brownout, reset (see Notes 1 and 2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
d(BOR)
2000
μ
s
V
CC(start)
dV
CC
/dt
≤
3 V/s (see Figure 6) 0.7
×
V
(B_IT−)
V
V
(B_IT−)
Brownout
dV
CC
/dt
≤
3 V/s (see Figure 6, Figure 7, and Figure 8) 1.71 V
V
hys(B_IT−)
Brownout
dV
CC
/dt
≤
3 V/s (see Figure 6) 70 130 180 mV
t
(reset)
Pulse length needed at RST/NMI pin to accepted reset internally,
V
CC
= 3 V
2
μ
s
NOTES: 1. The current consumption of the brownout module is already included in the I
CC
current consumption data. The voltage level
V
(B_IT−)
+ V
hys(B_IT−)
is
≤
1.8 V.
2. During power up, the CPU begins code execution following a period of t
d(BOR)
after V
CC
= V
(B_IT−)
+ V
hys(B_IT−)
.
The default FLL+ settings must not be changed until V
CC
≥
V
CC(min)
, where V
CC(min)
is the minimum supply voltage for the desired
operating frequency. See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout/SVS circuit.