Texas Instruments MSP430C311S Manual Download Page 27

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MSP430x31x

MIXED SIGNAL MICROCONTROLLERS

SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

POST OFFICE BOX 1443

•

HOUSTON, TEXAS 77251−1443

PMS430E313

†

, PMS430E315 (FZ package)

28 29

NC
S23/O23
S22/O22
S18/O18
S17/O17
S16/O16
S15/O15
S14/O14
S13/O13
S12/O12
S11/O11
S10/O10
S9/O9
S8/O8
S7/O7
NC
NC

NC
NC

R23
R13

Xin

Xout/TCLK

P0.0

P0.1/RXD

P0.2/TXD

P0.3
P0.4
P0.5
P0.6
P0.7

TP0.0

31 32 33 34

FZ PACKAGE

(TOP VIEW)

COM3

COM2

8 7

XBUF

RST/NMI

TCK

TMS

TDI/VPP

TDO/TDI

S2/O2

S3/O3

S4/O4

TP0.1

TP0.2

TP0.3

TP0.4

TP0.5

Cin

1 68 67

35 36 37 38 39

66 65

COM1

COM0

64 63 62 61

40 41 42 43

S5/O5

S6/O6

S27/O27/CMPI

S26/O26

NC − No internal connection

†

MSP430P313/E313 not recommended for new designs − replaced by MSP430P315/E315.

Summary of Contents for MSP430C311S

Page 1: ...onstant generator the MSP430 achieves maximum code efficiency The digitally controlled oscillator together with the frequency locked loop FLL provides a wakeup from a low power mode to active mode in less than 6 ms MSP430P313 E313 not recommended for new designs replaced by MSP430P315 E315 Please be aware that an important notice concerning availability standard warranty and use in critical applic...

Page 2: ...DL MSP430P315SIDL MSP430C314IDL MSP430C315IDL MSP430P313IDL MSP430P315IDL 25 C PMS430E313FZ 25 C PMS430E313FZ PMS430E315FZ MSP430P313 E313 not recommended for new designs replaced by MSP430P315 E315 functional block diagram MSP430C312 313 314 315 and MSP430P313 315 and PMS430E313 315 Oscillator FLL System Clock ACLK MCLK 4 8 12 16 kB ROM 8 16 kB C ROM 256 512 B RAM Power On Reset 8 Bit Timer Count...

Page 3: ...t port O14 to O17 group 4 LCD S18 O18 47 O Segment line S18 or digital output port O18 group 5 LCD S22 O22 S23 O23 48 49 O Segment lines S22 to S23 or digital output port O22 to O23 group 6 LCD S26 O26 50 O Segment line S26 or digital output port O26 group 7 LCD S27 O27 CMPI 51 I O Segment line S27 or digital output port O27 group 7 can be used as a comparator input port CMPI timer port TCK 4 I Te...

Page 4: ... kB ROM 16 kB C ROM 128 512B RAM Power On Reset 8 bit Timer Counter Serial Protocol I O Port 6 I O s All With Interr Cap 2 Int Vectors CPU Incl 16 Reg Test JTAG Bus Conv Timer Port Applications Timer O P Basic LCD 64 Segments 1 2 3 4 MUX Timer1 Watchdog Timer 15 16 Bit MAB 16 Bit MDB 16 Bit MAB 4 Bit MDB 8 Bit MCB 4 LCD f CMPI TP0 0 3 CIN XIN Xout XBUF RST NMI COM0 3 S2 16 O2 16 S27 O27 CMPI R13 R...

Page 5: ... port O6 to O9 group 2 LCD S10 O10 S13 O13 33 36 O Segment lines S10 to S13 or digital output port O10 to O13 group 3 LCD S14 O14 S16 O16 37 39 O Segment lines S14 to S17 or digital output port O14 to O17 group 4 LCD S27 O27 CMPI 43 I O Segment line S27 or digital output port O27 group 7 can be used as a comparator input port CMPI timer port TCK 3 I Test clock TCK is a clock input terminal for dev...

Page 6: ...es are available as general purpose registers Peripherals connected to the CPU using a data address and control bus can be handled easily with all instructions for memory manipulation instruction set The instruction set for this register register architecture provides a powerful and easy to use assembly language The instruction set consists of 51 instructions with three formats and seven addressin...

Page 7: ...rns with the RETI instruction to the mode that was selected before the interrupt event The clocks used are ACLK and MCLK ACLK is the crystal frequency and MCLK a multiple of ACLK is used as the system clock The software can configure five operating modes D Active mode AM The CPU is enabled with different combinations of active peripheral modules D Low power mode 0 LPM0 The CPU is disabled peripher...

Page 8: ...instruction sequence INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power up external reset watchdog WDTIFG see Note 1 Reset 0FFFEh 15 highest NMI oscillator fault NMIIFG see Notes 1 and 3 OFIFG see Notes 1 and 4 Nonmaskable Non maskable 0FFFCh 14 Dedicated I O P0 0 P0 0IFG Maskable 0FFFAh 13 Dedicated I O P0 1 P0 1IFG Maskable 0FFF8h 12 8 Bit Timer Counter P0 1IFG Maskable...

Page 9: ...ble signal P0IE 0 Dedicated I O P0 0 P0IE 1 P0 1 or 8 Bit Timer Counter RXD 7 6 5 4 0 TPIE rw 0 3 2 1 rw 0 Address 01h BTIE TPIE Timer Port enable signal BTIE Basic Timer1 enable signal interrupt flag register 1 and 2 7 6 5 4 0 P0IFG 1 OFIFG WDTIFG 3 2 1 rw 0 rw 1 rw 0 Address 02h NMIIFG P0IFG 0 rw 0 rw 0 WDTIFG Set on overflow or security key violation OR Reset on VCC power on or reset condition ...

Page 10: ...DFh E000h 02FFh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h MSP430C313 Int Vector 8 kB OTP or EPROM 256B RAM 16b Per 8b Per SFR FFFFh FFE0h FFDFh E000h 02FFh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h MSP430P313 PMS430E313 Int Vector 16 kB ROM 512B RAM 16b Per 8b Per SFR FFFFh FFE0h FFDFh C000h 03FFh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h MSP430C315 Int Vector 4 kB ROM 256B RAM 16b Per 8b Per SFR ...

Page 11: ... to minimize current consumption EMI etc Stable frequency for timer applications e g real time clock RTC Enable start stop operation with a minimum delay These requirements cannot all be met with fast frequency high Q crystals or with RC type low Q oscillators The compromise selected for the MSP430 uses a low crystal frequency which is multiplied to achieve the desired nominal operating range f sy...

Page 12: ...driven directly The controller LCD logic operation is defined by software using memory bit manipulation LCD memory is part of the LCD module and not part of the data memory Eight mode and control bits define the operation and current consumption of the LCD drive The information for the individual digits can be easily obtained using table programming techniques combined with the correct addressing ...

Page 13: ...g to the function implemented in the Basic Timer1 These two bits are the Basic Timer1 interrupt flag BTIFG and the basic timer interrupt enable BTIE bit Watchdog Timer The primary function of the Watchdog Timer WDT module is to perform a controlled system restart after a software problem has occurred If the selected time interval expires a system reset is generated If this watchdog function is not...

Page 14: ... has elapsed UART The serial communication is realized by using software and the 8 bit timer counter hardware The hardware supports the output of the serial data stream bit by bit with the timing determined by the counter The software hardware interface connects the mixed signal controller to external devices systems or networks peripheral file map PERIPHERALS WITH WORD ACCESS Watchdog Watchdog Ti...

Page 15: ...s MIN NOM MAX UNIT MSP430Cxxx 2 5 5 5 Supply voltage VCC MSP430P313 PMS430E313 2 7 5 5 V Supply voltage VCC MSP430P315 PMS430E315 2 7 5 5 V Supply voltage during programming V MSP430P313 2 7 5 5 V Supply voltage during programming VCC MSP430P315 4 5 5 5 V Supply voltage VSS 0 V MSP430C31x 40 85 Operating free air temperature range TA MSP430P31x 40 85 C Operating free air temperature range TA PMS43...

Page 16: ...P315 S T 40 C 85 C VCC 3 V 490 550 P315 S TA 40 C 85 C VCC 5 V 960 1050 C31x T 40 C 85 C VCC 3 V 50 70 C31x TA 40 C 85 C VCC 5 V 100 130 I Low power mode LPM0 1 P313 T 40 C 85 C VCC 3 V 70 85 μA I CPUOff Low power mode LPM0 1 P313 TA 40 C 85 C VCC 5 V 150 170 μA P315 S T 40 C 85 C VCC 3 V 50 70 P315 S TA 40 C 85 C VCC 5 V 100 130 I Low power mode LPM2 T 40 C 85 C VCC 3 V 6 12 μA I LPM2 Low power m...

Page 17: ...VCC V High level output voltage IOH 3 5 mA VCC 3 V See Note 6 VCC 1 VCC V VOH High level output voltage IOH 1 5 mA VCC 5 V See Note 5 VCC 0 4 VCC V IOH 4 5 mA VCC 5 V See Note 6 VCC 1 VCC IOL 1 2 mA VCC 3 V See Note 5 VSS VSS 0 4 V Low level output voltage IOL 3 5 mA VCC 3 V See Note 6 VSS VSS 1 V VOL Low level output voltage IOL 1 5 mA VCC 5 V See Note 5 VSS VSS 0 4 V IOL 4 5 mA VCC 5 V See Note ...

Page 18: ...P313 E313 not recommended for new designs replaced by MSP430P315 E315 and P E315 s inputs P0 x CIN TP 5 output XBUF PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT t int External interrupt timing Port P0 External trigger signal for the interrupt flag see Notes 11 and 12 3 V 5 V 1 5 cycle f IN Input frequency 3 V 5 V DC f system MHz 3 V 5 V DC f system MHz t H or t L High level or low level time P0 ...

Page 19: ...FN 4 FN 3 0 FN 2 1 VCC 3 V 2 5 8 1 MHz fDC26 NDCO 11 0100 0000 FN_4 FN_3 0 FN_2 1 VCC 5 V 3 9 9 f CO N CO 00 0110 0000 FN 4 0 FN 3 1 FN 2 X VCC 3 V 0 5 1 5 3xf fDCO3 NDCO 00 0110 0000 FN_4 0 FN_3 1 FN_2 X VCC 5 V 0 6 1 8 MHz 3xf NOM f N 11 0100 0000 FN 4 0 FN 3 1 FN 2 X VCC 3 V 3 7 11 MHz fDCO26 NDCO 11 0100 0000 FN_4 0 FN_3 1 FN_2 X VCC 5 V 4 5 13 8 f N 00 0110 0000 FN 4 1 FN 3 FN 2 X VCC 3 V 0 7...

Page 20: ...V 33 kΩ NOTE 13 I IRxx is measured with no load on the segment or common LCD I O pins comparator Timer Port PARAMETER TEST CONDITIONS MIN NOM MAX UNIT I Comparator timer port CPON 1 VCC 3 V 250 350 A I com Comparator timer port CPON 1 VCC 5 V 450 600 μA Vref com Internal reference voltage at terminal CPON 1 VCC 3 V 5 V 0 230 VCC 0 25 VCC 0 260 VCC V V Input hysteresis comparator CPON 1 VCC 3 V 5 3...

Page 21: ... POR V t V POR V min POR No POR Figure 4 Power On Reset POR vs Supply Voltage 1 8 2 1 2 4 0 9 1 2 1 5 0 0 5 1 1 5 2 2 5 3 40 20 0 20 40 60 80 Temperature C 25 C V POR V Figure 5 V POR vs Temperature wakeup from LPM3 PARAMETER TEST CONDITIONS MIN NOM MAX UNIT f 1 MHz VCC 3 V 6 f 1 MHz VCC 5 V 6 t LPM3 Delay time f 2 MHz VCC 3 V 6 μs LPM3 y f 2 MHz VCC 5 V 6 μ f 3 MHz VCC 5 V 6 ...

Page 22: ...to blow the fuse 1 ms V P313 E313 Programming voltage applied to TDI VPP 11 11 5 13 V V PP P315 S E315 Programming voltage applied to TDI VPP 12 12 5 13 V I PP Current from programming voltage source 70 mA t pps EPROM E and OTP P versions only Programming time single pulse 5 ms t ppf versions only see Note 18 Programming time fast algorithm 100 μs Pn see Note 18 Pulses for successful programming 4...

Page 23: ...ncreasing overall system power consumption Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low after power up The second positive edge on the TMS pin deactivates the fuse check mode After deactivation the fuse check mode remains inactive until another POR occurs After each POR the fuse check mode has the potential to b...

Page 24: ...EXAS 77251 1443 TYPICAL CHARACTERISTICS Figure 7 DIGITAL CONTROLLED OSCILLATOR FREQUENCY vs OPERATING FREE AIR TEMPERATURE T Operating Free Air Temperature C 0 9 0 6 0 3 0 1 2 1 5 1 8 f DCO f DCO 25 C 40 20 0 20 40 90 60 80 Figure 8 VCC Supply Voltage V 0 6 0 4 0 2 0 0 2 0 8 1 1 2 4 6 DIGITAL CONTROLLED OSCILLATOR FREQUENCY vs SUPPLY VOLTAGE f DCO f DCO 3 V ...

Page 25: ... 4 XBUF VCC see Note A see Note A GND VCC see Note A see Note A GND VCC see Note A see Note A GND VCC 60 k TYP MSP430C31x TMS TCK MSP430P E31x TMS TCK NOTES A Optional selection of pull up or pull down resistors with ROM masked versions B Fuses for the optional pull up and pull down resistors can only be programmed at the factory CMOS SCHMITT TRIGGER INPUT CIN MSP430C31x TDO TDI MSP430P E31x TDO T...

Page 26: ...I_ Internal TDO TDI_Control TDO_ Internal From To JTAG_CBT_SIG_REG NOTES A During programming activity and when blowing the JTAG enable fuse the TDI VPP terminal is used to apply the correct voltage source The TDO TDI terminal is used to apply the test input data for JTAG circuitry B The TDI VPP terminal of the P31x and E31x does not have an internal pullup resistor An external pulldown resistor i...

Page 27: ... 52 51 50 49 48 47 46 45 44 30 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 NC NC VCC R23 R13 Xin Xout TCLK P0 0 P0 1 RXD P0 2 TXD P0 3 P0 4 P0 5 P0 6 P0 7 TP0 0 NC 31 32 33 34 FZ PACKAGE TOP VIEW COM3 COM2 8 7 6 5 4 9 3 XBUF RST NMI TCK TMS TDI VPP TDO TDI S1 S2 O2 S3 O3 S4 O4 TP0 1 TP0 2 TP0 3 TP0 4 TP0 5 Cin S0 1 68 67 2 35 36 37 38 39 66 65 27 NC NC COM1 COM0 64 63 62 61 40 41 42 43 S5 O...

Page 28: ...2 12 57 0 495 0 455 11 56 10 92 0 430 MAX MIN B C MIN MAX 0 410 10 41 10 92 0 430 0 630 0 610 0 630 0 655 0 695 0 685 16 00 15 49 16 00 16 64 17 65 17 40 0 740 0 680 0 730 0 765 0 795 0 785 18 79 17 28 18 54 19 43 20 19 19 94 PINS 28 44 52 NO OF JEDEC MO 087AC MO 087AB MO 087AA OUTLINE 28 LEAD SHOWN Seating Plane at Seating Plane 1 4 26 25 19 18 12 11 5 0 050 1 27 0 930 0 910 0 930 0 955 0 995 0 9...

Page 29: ...defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This compone...

Page 30: ... better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for r...

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Page 33: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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