6.2 Single-Ended Input
for proper setup of a single-ended input.
Table 6-1. Single-Ended Configurations by Bias Voltage
BIAS VOLTAGE
TO INx_N (V)
INPUT TO INx_P
(V)
INPUT
REMOVE
BIASING
RESISTOR
REMOVE
COMMON-MODE
RESISTOR
REPLACE WITH
0-Ω RESISTOR
REPLACE WITH
100-Ω RESISTOR
0.9
1.8 (LVCMOS)
IN0_N
R5
R6
R12
C3
N/A
IN0_P
C4
N/A
0.9
1.8 (LVCMOS)
IN1_N
R7
R8
R13
C5
N/A
IN1_P
C6
N/A
1.25
2.5 (LVCMOS)
IN0_N
R6
R12
R1
C3, C4
R14
R15
IN0_P
1.25
2.5 (LVCMOS)
IN1_N
R8
R13
R2
C5, C6
R16
R17
IN1_P
1.65
3.3 (LVCMOS)
IN0_N
R6
R12
R1
C3, C4
R14
R15
IN0_P
1.65
3.3 (LVCMOS)
IN1_N
R8
R13
R2
C5, C6
R16
R17
IN1_P
Input Clock
SNAU270 – FEBRUARY 2022
LMK1D1208IEVM User's Guide
7
Copyright © 2022 Texas Instruments Incorporated