GND
1
2
3
4
5
J1
CON-SMA-EDGE-S
GND
1
2
3
4
5
J2
CON-SMA-EDGE-S
49.9
R5
49.9
R6
VAC_REF0/NC
0
R12
GND
1uF
R1
1uF
C7
0.1µF
C3
0.1µF
C4
VCC
49.9
R14
VCC
49.9
R15
GND
1
2
3
4
5
J3
GND
1
2
3
4
5
J4
CON-SMA-EDGE-S
49.9
R7
49.9
R8
VAC_REF1/NC
0
R13
GND
1uF
R2
1uF
C8
0.1µF
C5
0.1µF
C6
VCC
49.9
R16
VCC
49.9
R17
INN0
INP1
INP0
INN1
INP0
INN0
INP1
INN1
Default: AC-coupled LVDS inputs for IN0 and IN1
VAC_REF1/NC
VAC_REF0/NC
0
R19
0
R18
PBC03SAAN
1
2
3
J5
GND
SDA_BACK
SDA1
SCL1
1.00k
R20
VCC
1.00k
R21
VCC
SCL_BACK
SDA1
SCL1
GND
10pF
50V
C9
GND
10pF
50V
C10
1.5k
R9
U2A_3V3
1.5k
R4
100nF
16V
C2
GND
10V
1uF
C1
GND
510
R3
Yellow
1
2
D1
S
D
A
S
C
L
0
R10
0
R11
U2AGPIO0
U2AGPIO1
TP2
TP1
PBC03SAAN
1
2
3
J6
GND
0
R22
IDX1
IDX1
PBC03SAAN
1
2
3
J9
0
R23
IDX0
IDX0
GND
VCC
VCC
CON-SMA-EDGE-S
Default: I2C connection through USB2ANY
Default: 0x6B when floating (internal 650 kΩ pullup on IDX pins)
I2C Address Configuration
IDX1
IDX0
L
H
L
L
L
H
H
H
Address
0x68
0x69
0x6A
0x6B
Figure 9-2. LMK1D1208IEVM Schematic: Inputs Sheet
EVM Board Schematic
SNAU270 – FEBRUARY 2022
LMK1D1208IEVM User's Guide
13
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