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Quick Start
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SNAU200 – September 2016
Copyright © 2016, Texas Instruments Incorporated
LMK04208 User’s Guide
3.1
Quick Start Description
The LMK04208 EVM allows full verification of the device functionality and performance specifications. To
quickly set up and operate the board with basic equipment, refer to the quick start procedure below and
test setup shown in
.
1. Connect a voltage of
4.5
volts to the Vcc SMA connector or terminal block. Device operates at 3.3 V
using onboard LP3878-ADJ LDO. VCXO operates at 3.3 V using onboard LP5900 LDO.
2. Connect a reference clock to the CLKin1 port from a signal generator or other source. Use
122.88 MHz
for default. Exact frequency and input port (CLKin0/CLKin1) depends on programming.
3. Connect uWire (MICROWIRE) header to a computer using USB2ANY.
4. Program the device with TICS Pro. TICS Pro is available for download at:
. After starting TICS Pro.
(a) Choose LMK04208 from the “Select Device"
→
"Clock Generator/Jitter Cleaner (Dual Loop)” Menu.
(b) Open the Communication Setup window by click "USB Communications
→
Interface".
•
Confirm that USB2ANY is selected.
•
Select specific USB2ANY interface to use. click 'Identify' to confirm selected USB2ANY and
valid communications to USB2ANY by blinking LED.
•
If LMK04208EVM or USB2ANY available, the software may be run in DemoMode for evaluation
and generation of register programming data.
•
Press Close to exit Communication Setup.
(c) From menu bar click "Default configuration" to select a default mode. For the quick start use,
“
CLKin1 122.88 MHz, 122.88 MHz VCXO
”
(d) Click "Write All Registers" or press
Ctrl-L
to load all registers. Alternatively from menu bar click
"USB communications"
→
"Write All Registers."
5. Measurements may be made at an active CLKout port via its SMA connector. Default configuration
configures CLKout4
3.1.1
CLKout Page Description
Figure 2. Clock Outputs Page CLKout Path Description Diagram
1. CLKoutX_DDLY for controlling digital delay. Programmed delay value takes effect on SYNC of divider.
2. CLKoutX_HS for finer resolution of digital delay. Advances waveform ½ device clock cycles, -0.5 to
digital delay.
3. CLKoutX_DIV, divider for the output channel.
4. CLKoutX_ADLY, Analog delay if enabled with #5.
5. CLKoutX_ADLY_SEL, Analog delay select.
6. CLKoutX_TYPE, clock output format.
7. NO_SYNC_CLKoutX, when checked, output will never be SYNCed or held in SYNC.
8. Clock output identifier.
9. Calculated clock output frequency.
10. CLKoutX_PD, power down the entire CLKoutX group.
