Evaluation Board Inputs and Outputs
12
SNAU200 – September 2016
Copyright © 2016, Texas Instruments Incorporated
LMK04208 User’s Guide
Table 5. Description of Evaluation Board Inputs and Outputs (continued)
CONNECTOR NAME
SIGNAL TYPE,
INPUT/OUTPUT
DESCRIPTION
Populated:
CLKin0, CLKin0*,
FBCLKin*/CLKin1*
Analog,
Input
Reference Clock Inputs for PLL1 (CLKin0, CLKin1)
CLKin0/CLKin0* is configured by default for a differential reference clock input from
a 50-ohm source.
FBCLKin*/CLKin1* is configured by default for a single-ended reference clock input
from a 50-ohm source using a 3 dB pad for termination which is recommended for
high speed inputs. The unused input pin (FBCLKin/CLKin1) is connected to GND
with a 0.1 µF.
CLKin1 is the default reference clock input selected in TICS Pro. The clock input
selection mode can be programmed on the
CLKins and PLLs
page via the Clock
Inputs control.
CLKin1 as External Feedback Input (FBCLKin) for 0-Delay
CLKin1 is shared for use with FBCLKin as an external feedback clock input to PLL1
for 0-delay mode.
CLKin1 as Fin for external VCO or Clock Distribution mode
CLKin1 be used as an RF Input (Fin) for External VCO for PLL2 or for an input in
Clock Distribution mode.
Not Populated:
OSCin, OSCin*
Analog,
Input
OSCin is the feedback clock input to PLL1 and reference clock input to PLL2. The
onboard VCXO drives OSCin by default for dual loop operation.
By default the differential output of the LVPECL VCXO (U8) or the single-ended
output of the onboard VCXO (U2) drives the OSCin input of the device. When using
a single ended VCXO the OSCin* port is driven and the non-inverting OSCin input
of the device is connected to GND with 0.1 µF.
An external VCXO may be optionally attached via these SMA connectors with minor
modification to the components going to the OSCin/OSCin* pins of device. This is
useful if the VCXO footprint does not accommodate the desired VCXO device or if
the user desires to use the LMK04208 in single loop mode. It is also necessary to
connect the Vtune input of the VCXO to the CPout1.
A single-ended or differential signal may be used to drive the OSCin/OSCin* pins
and must be AC coupled. If operated in single-ended mode, the unused input must
be connected to GND with 0.1 µF.
Refer to the LMK04802 datasheet section “Electrical Characteristics” for PLL2
Reference Input (OSCin) specifications (literature number
Test point:
VTUNE1_TP
Analog,
Input
Tuning voltage monitor for the loop filter for PLL1.
Test point:
VTUNE2_TP
Analog,
Input
Tuning voltage monitor for the loop filter for PLL2.
Test points:
DATA
CLK
LE
CMOS,
Input
10-pin header for MICROWIRE™ programming interface and programmable logic
I/O pins for the LMK04208.
Populated:
uWire
10-pin header for SPI programming interface and programmable logic I/O pins for
the LMK04208.
The programmable logic I/O signals accessible through this header include: SYNC,
Status_LD, Status_Holdover, Status_CLKin0, and Status_CLKin1. These logic I/O
signals also have dedicated SMAs and test points.
Test point:
LD_TP
CMOS,
Input/Output
Programmable status output pin. By default, set to output the digital lock detect
status signal for PLL1 & PLL2 DLD.
In the default TICS Pro modes, LED D1 will illuminate green when PLL1 and PLL2
lock is detected by the LMK04208 (output is high) and turn off when lock is lost
(output is low).
Status_LD pin 33
The status output signal for the Status_LD pin can be selected on the
User
Controls
page via the LD_MUX and LD_TYPE controls.
For debugging purposes, it is suggested to set LD_MUX/Status_LD to output
PLL1 DLD and HOLDOVER_MUX/Status_Holdover to output PLL2 DLD
individually. In holdover mode PLL1 DLD will normally be low but may flicker
high momentarily.
